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AgeCommit message (Expand)Author
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
2025-11-19scsi: fnic: Switch to use %ptSpAndy Shevchenko
2025-11-19s390/dasd: Switch to use %ptSpAndy Shevchenko
2025-11-19ptp: ocp: Switch to use %ptSpAndy Shevchenko
2025-11-19pps: Switch to use %ptSpAndy Shevchenko
2025-11-19PCI: epf-test: Switch to use %ptSpAndy Shevchenko
2025-11-19net: dsa: sja1105: Switch to use %ptSpAndy Shevchenko
2025-11-19mmc: mmc_test: Switch to use %ptSpAndy Shevchenko
2025-11-19media: av7110: Switch to use %ptSpAndy Shevchenko
2025-11-19ipmi: Switch to use %ptSpAndy Shevchenko
2025-11-19igb: Switch to use %ptSpAndy Shevchenko
2025-11-19e1000e: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/vblank: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Add PLL information for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Add macro to get DDI port width from a register valueImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-19drm/i915/cx0: Rename TBT functions to be ICL specificMika Kahola
2025-11-19gpio: cdev: make sure the cdev fd is still active before emitting eventsBartosz Golaszewski
2025-11-19pwm: bcm2835: Make sure the channel is enabled after pwm_request()Uwe Kleine-König
2025-11-19drm/msm: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/amdgpu: Switch to use %ptSpAndy Shevchenko
2025-11-19dma-buf: Switch to use %ptSpAndy Shevchenko
2025-11-19drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian
2025-11-19gpio: shared: extend the ifdef guard to gpio_shared_find_entry()Bartosz Golaszewski
2025-11-19gpio: shared: fix a NULL-pointer dereferenceBartosz Golaszewski
2025-11-18drm/xe/vf: Shadow buffer management for CCS read/write operationsSatyanarayana K V P
2025-11-18drm/xe/sa: Shadow buffer support in the sub-allocator poolSatyanarayana K V P
2025-11-18net/mlx5: Use EOPNOTSUPP instead of ENOTSUPPTariq Toukan
2025-11-18net/mlx5: Abort new commands if all command slots are stalledSaeed Mahameed
2025-11-18net/mlx5: Remove redundant bw_share minimal value assignmentCarolina Jubran
2025-11-18net/mlx5e: Recover SQ on excessive PTP TX timestamp deltaCarolina Jubran
2025-11-18net/mlx5: Refactor EEPROM query error handling to return status separatelyGal Pressman
2025-11-18net/mlx5: Clean up only new IRQ glue on request_irq() failurePradyumn Rahar
2025-11-18hwmon: (k10temp) Add AMD Steam Deck APU IDRené Rebe
2025-11-18hwmon: Add Apple Silicon SMC hwmon driverJames Calligeros
2025-11-18net: dsa: ks8995: Fix incorrect OF match table nameAlok Tiwari
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