summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
AgeCommit message (Expand)Author
2014-04-02drm/i915: Add intel_ring_cachline_align()Ville Syrjälä
2013-09-10drm/i915: Invalidate TLBs for the rings after a resetChris Wilson
2013-06-29Revert "drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanlin...Ben Hutchings
2013-02-06drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waitsChris Wilson
2013-02-06drm/i915: Disable AsyncFlip performance optimisationsChris Wilson
2013-02-06drm/i915: Remove the MI_FLUSH_ENABLE setting.Eric Anholt
2012-08-19drm/i915: correctly order the ring init sequenceDaniel Vetter
2012-08-19drm/i915: Add wait_for in init_ring_commonSean Paul
2012-08-19drm/i915: fixup seqno allocation logic for lazy_requestDaniel Vetter
2012-07-04drm/i915: Remove use of the autoreported ringbuffer HEAD positionChris Wilson
2012-06-19drm/i915: hold forcewake around ring hw initDaniel Vetter
2012-06-19drm/i915: Mark the ringbuffers as being in the GTT domainChris Wilson
2012-05-11drm/i915: Do no set Stencil Cache eviction LRA w/a on gen7+Daniel Vetter
2012-05-11drm/i915: Set the Stencil Cache eviction policy to non-LRA mode.Kenneth Graunke
2012-05-11drm/i915: Force sync command ordering (Gen6+)Ben Widawsky
2012-04-22drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845gChris Wilson
2012-02-03drm/i915: paper over missed irq issues with force wake voodooDaniel Vetter
2011-10-20drm/i915: Use PIPE_CONTROL for flushing on gen6+.Jesse Barnes
2011-10-20drm/i915: Rename PIPE_CONTROL bit defines to be less terse.Kenneth Graunke
2011-10-20drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define.Kenneth Graunke
2011-09-21drm/i915: Dumb down the semaphore logicBen Widawsky
2011-09-19Drivers: i915: Fix all space related issues.Akshay Joshi
2011-08-19drm/i915: set GFX_MODE to pre-Ivybridge default value even on IvybridgeJesse Barnes
2011-07-22Merge branch 'drm-intel-fixes' into drm-intel-nextKeith Packard
2011-07-22drm/i915: Initialize RCS ring status page address in intel_render_ring_init_driKeith Packard
2011-06-09drm/i915: Add an interface to dynamically change the cache levelChris Wilson
2011-05-16drm/i915: clean up unused ring_get_irq/ring_put_irq functionsFeng, Boqun
2011-05-16drm/i915: fix user irq miss in BSD ring on g4xFeng, Boqun
2011-05-13drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.Eric Anholt
2011-05-13drm/i915: ring support for Ivy BridgeJesse Barnes
2011-05-10drm/i915: Rename agp_type to cache_levelChris Wilson
2011-05-10drm/1915: ringbuffer wait for idle functionBen Widawsky
2011-05-10drm/i915: Move the irq wait queue initialisation into the ring initChris Wilson
2011-03-23drm/i915: Restore missing command flush before interrupt on BLT ringChris Wilson
2011-02-16Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
2011-02-07drm/i915: Refine tracepointsChris Wilson
2011-02-02drm/i915: Invalidate TLB caches on SNB BLT/BSD ringsChris Wilson
2011-01-27drm/i915: Defer reporting EIO until we try to use the GPUChris Wilson
2011-01-25drm/i915: Silence a few -Wunused-but-set-variableChris Wilson
2011-01-24Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
2011-01-20drm/i915/ringbuffer: Fix use of stale HEAD position whilst polling for spaceChris Wilson
2011-01-20drm/i915/ringbuffer: Kill an annoyingly frequent debug messageChris Wilson
2011-01-20drm/i915: Initialise ring vfuncs for old DRI pathsChris Wilson
2011-01-11drm/i915: Make the ring IMR handling privateChris Wilson
2011-01-11drm/i915/ringbuffer: Simplify the ring irq refcountingChris Wilson
2011-01-11drm/i915: Mask USER interrupts on gen6 (until required)Chris Wilson
2011-01-11drm/i915: Handle ringbuffer stalls when flushingChris Wilson
2011-01-11drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelinesChris Wilson
2010-12-15Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"Chris Wilson
2010-12-14drm/i915/ringbuffer: Make IRQ refcnting atomicChris Wilson
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-11 01:59:51 +0000