kernel.git - Hosts the 0x221E linux distro kernel.

Age	Commit message (Expand)	Author
2026-01-17	clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114	Svyatoslav Ryhel
2026-01-17	clk: tegra20: Reparent dsi clock to pll_d_out0	Svyatoslav Ryhel
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring
2023-03-29	clk: tegra20: fix gcc-7 constant overflow warning	Arnd Bergmann
2022-10-14	clk: tegra: Fix Tegra PWM parent clock	Jon Hunter
2022-08-22	clk: tegra20: Fix refcount leak in tegra20_clock_init	Miaoqian Lin
2021-12-15	clk: tegra: Support runtime PM and power domain	Dmitry Osipenko
2021-05-31	clk: tegra: Halve SCLK rate on Tegra20	Dmitry Osipenko
2020-05-12	clk: tegra20: Use custom CCLK implementation	Dmitry Osipenko
2020-03-12	clk: tegra: Remove audio clocks configuration from clock driver	Sowjanya Komatineni
2020-03-12	clk: tegra: Remove tegra_pmc_clk_init along with clk ids	Sowjanya Komatineni
2020-01-10	clk: tegra20/30: Explicitly set parent clock for Video Decoder	Dmitry Osipenko
2020-01-10	clk: tegra20/30: Don't pre-initialize displays parent clock	Dmitry Osipenko
2019-11-11	clk: tegra: Optimize PLLX restore on Tegra20/30	Dmitry Osipenko
2019-11-11	clk: tegra: Add Tegra20/30 EMC clock implementation	Dmitry Osipenko
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner
2018-11-08	clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC	Dmitry Osipenko
2018-11-08	clk: tegra20: Turn EMC clock gate into divider	Dmitry Osipenko
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko
2018-05-18	clk: tegra20: Correct parents of CDEV1/2 clocks	Dmitry Osipenko
2018-05-18	clk: tegra20: Add DEV1/DEV2 OSC dividers	Dmitry Osipenko
2018-03-12	clk: tegra: Specify VDE clock rate	Dmitry Osipenko
2018-03-12	clk: tegra20: Correct PLL_C_OUT1 setup	Dmitry Osipenko
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko
2017-11-01	clk: tegra: Bump SCLK clock rate to 216 MHz	Dmitry Osipenko
2017-11-01	clk: tegra: Use common definition of APBDMA clock gate	Dmitry Osipenko
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding
2016-04-28	treewide: Fix typos in printk	Masanari Iida
2016-03-02	clk: tegra: Remove CLK_IS_ROOT	Stephen Boyd
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding
2015-11-18	clk: tegra: Format tables consistently	Thierry Reding
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding
2014-02-17	clk: tegra: Add missing Tegra20 fuse clks	Peter De Schrijver
2013-12-11	clk: tegra: remove bogus PCIE_XCLK	Stephen Warren
2013-12-11	clk: tegra: implement a reset driver	Stephen Warren
2013-11-26	clk: tegra: add FUSE clock device	Alexandre Courbot
2013-11-26	clk: tegra: move tegra20 to common infra	Peter De Schrijver
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver
2013-11-26	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver
2013-11-26	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver
2013-11-26	clk: tegra: simplify periph clock data	Peter De Schrijver
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan
2013-08-08	clk: tegra20: Fix incorrect placement of __initdata	Sachin Kamat
2013-05-31	clk: tegra: Use common of_clk_init function	Prashant Gaikwad
2013-05-20	clk: tegra: add ac97 controller clock	Lucas Stach