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| author | Sowjanya Komatineni | 2020-05-04 19:31:52 -0700 |
|---|---|---|
| committer | Thierry Reding | 2020-05-20 15:26:09 +0200 |
| commit | b4f99176a501ac34c7f5c9322910e248a2f43397 (patch) | |
| tree | 66287ece150a924027ff7e8fe446ad753bebd532 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4012ab12b3cbd3efbd7254f04de40903c624a237 (diff) | |
arm64: tegra: Fix SOR powergate clocks and reset
Tegra210 device tree lists CSI clock and reset under SOR powergate
node.
But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.
So, this patch includes fix for SOR powergate node.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions