diff options
| author | Konrad Dybcio | 2025-06-26 11:02:34 +0200 |
|---|---|---|
| committer | Rob Clark | 2025-07-04 17:48:40 -0700 |
| commit | 87cfc79dcd605056247c62d65ea41ce6c65cdbe3 (patch) | |
| tree | cb96eb04d93ccd1dfcbe4d9884d61e9ebc83c4bc /drivers/gpu/drm | |
| parent | 32ef24e51f7ff4dd5eaeb3e0f06f0ad36143bdc6 (diff) | |
drm/msm/a6xx: Resolve the meaning of UBWC_MODE
This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".
This commit is intentionally cross-subsystem to ease review, as the
patchset is intended to be merged together, with a maintainer
consensus.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660971/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1d541416a4cb..f998dc240d49 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -687,11 +687,11 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) */ BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; + bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0; u8 uavflagprd_inv = 0; u32 hbb_hi = hbb >> 2; u32 hbb_lo = hbb & 3; - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) |