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authorDaniele Ceraolo Spurio2024-04-19 11:34:12 -0700
committerDaniele Ceraolo Spurio2024-05-01 10:47:20 -0700
commita1ea30b69e02eb02043b0d6d7c42abcfafe99bd0 (patch)
tree5435267d0953dd0962aded67a325f9259b6fc964
parentd457519c942d4885d92f6367e42ca67f4c7471ad (diff)
drm/xe/gsc: define GSCCS for LNL
LNL has 1 GSCCS, same as MTL. Note that the GSCCS will be disabled until we have a GSC FW defined, but having it in the list of engine is a requirement to add such definition. v2: rebase Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240419183412.1605782-2-daniele.ceraolospurio@intel.com
-rw-r--r--drivers/gpu/drm/xe/xe_pci.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index fb20c9828563..d0d4d8f9749c 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -211,7 +211,8 @@ static const struct xe_media_desc media_xe2 = {
.name = "Xe2_LPM / Xe2_HPM",
.hw_engine_mask =
GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
- GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), /* TODO: GSC0 */
+ GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
+ BIT(XE_HW_ENGINE_GSCCS0)
};
static const struct xe_device_desc tgl_desc = {