diff options
| author | Takeshi Kihara | 2017-06-01 22:25:30 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven | 2017-07-17 10:51:32 +0200 |
| commit | 1554b989e58c8e5327da5391ea66b6b166f09d8e (patch) | |
| tree | cfbe3c22dbe0a8dce7df1cfb20d9dd94ead0699d | |
| parent | 70070190871f831ceb46cce6c2b9a1038d1802cf (diff) | |
pinctrl: sh-pfc: r8a7796: Fix IPSR setting for MSIOF3_SS1_E pin
This patch fixes the IPSR register setting when the MSIOF3_SS1_E pin
function is selected.
This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 6fa1729d784e..0fd96f198b4d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -645,7 +645,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), - PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), + PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), /* IPSR1 */ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), |