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AgeCommit message (Expand)Author
2025-09-21mmc: drop nth_page() usage within SG entryDavid Hildenbrand
2025-09-21memstick: drop nth_page() usage within SG entryDavid Hildenbrand
2025-09-21mspro_block: drop nth_page() usage within SG entryDavid Hildenbrand
2025-09-21drm/i915/gem: drop nth_page() usage within SG entryDavid Hildenbrand
2025-09-21ata: libata-sff: drop nth_page() usage within SG entryDavid Hildenbrand
2025-09-21Merge branch 'mm-hotfixes-stable' into mm-stable in order to pick upAndrew Morton
2025-09-21reset: aspeed: register AST2700 reset auxiliary bus deviceRyan Chen
2025-09-21clk: tegra: do not overallocate memory for bpmp clocksFedor Pchelkin
2025-09-21clk: ep93xx: Use int type to store negative error codesQianfeng Rong
2025-09-21clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driverAlok Tiwari
2025-09-21clk: loongson2: Add clock definitions for Loongson-2K0300 SoCYao Zi
2025-09-21clk: loongson2: Avoid hardcoding firmware name of the reference clockYao Zi
2025-09-21clk: loongson2: Allow zero divisors for dividersYao Zi
2025-09-21clk: loongson2: Support scale clocks with an alternative modeYao Zi
2025-09-21clk: loongson2: Allow specifying clock flags for gate clockYao Zi
2025-09-21Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2025-09-21clk: clocking-wizard: Fix output clock register offset for Versal platformsShubhrajyoti Datta
2025-09-21clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()Shubhrajyoti Datta
2025-09-21clk: mmp: pxa1908: Instantiate power driver through auxiliary busDuje Mihanović
2025-09-21clk: s2mps11: add support for S2MPG10 PMIC clockAndré Draszik
2025-09-21clk: stm32: introduce clocks for STM32MP21 platformGabriel Fernandez
2025-09-21clk: Use hashtable for global clk lookupsChen-Yu Tsai
2025-09-21clk: Sort include statementsChen-Yu Tsai
2025-09-21clk: st: flexgen: remove unused compatibleRaphael Gallais-Pou
2025-09-21clk: mediatek: Add MT8196 vencsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 vdecsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ovl1 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ovl0 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp-ao clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp1 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 disp0 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mfg clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mdpsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 mcu clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 I2C clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 pextpsys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 ufssys clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 peripheral clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 vlpckgen clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 topckgen2 clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 topckgen clock supportLaura Nao
2025-09-21clk: mediatek: Add MT8196 apmixedsys clock supportLaura Nao
2025-09-21clk: mediatek: clk-mtk: Add MUX_DIV_GATE macroLaura Nao
2025-09-21clk: mediatek: clk-gate: Add ops for gates with HW voterLaura Nao
2025-09-21clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate structLaura Nao
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENCLaura Nao
2025-09-21clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()Laura Nao
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENCLaura Nao
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao