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path: root/drivers/spi
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2025-09-18spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHzHaibo Chen
Preparation of supportting DTR mode. In nor suspend, driver will disable DTR mode, and enable DTR mode back in nor resume. This require the flexspi driver has the ability to set back to dll override mode in STR mode when clock rate < 100MHz. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-2-bb9fe2a01889@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-18spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()Haibo Chen
Extract function nxp_fspi_dll_override(), this is the suggested setting when clock rate < 100MHz. Just the preparation of supportting DTR mode. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-1-bb9fe2a01889@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-18spi: atmel-quadspi: Add support for sama7d65 QSPIVarshini Rajendran
Add support for sama7d65 QSPI controller and define its caps. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Link: https://patch.msgid.link/20250908-microchip-qspi-v2-5-8f3d69fdd5c9@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-18spi: atmel-quadspi: add support for SAM9X7 QSPI controllerVarshini Rajendran
Add support for the QuadSPI controller found on the SAM9X7 SoC. This controller does not implement pad calibration. It supports operation up to 100 MHz, and requires the GCK to run at twice the data rate. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://patch.msgid.link/20250908-microchip-qspi-v2-4-8f3d69fdd5c9@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-18spi: atmel-quadspi: add padcalib, 2xgclk, and dllon capabilitiesVarshini Rajendran
Introduce capability flags for SoC-specific variations of the QuadSPI controller: - has_padcalib: controller supports pad calibration - has_2xgclk: requires GCLK at half the data rate (2x clocking) - has_dllon: controller supports DLL clock Set `has_padcalib` for Octal controllers that provide pad calibration support. Use `has_2xgclk` for controllers that require the GCLK to run at twice the data rate. Differentiate SoC integration variants with the `has_dllon` flag and set it as needed. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://patch.msgid.link/20250908-microchip-qspi-v2-3-8f3d69fdd5c9@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-18spi: cadence-qspi: defer runtime support on socfpga if reset bit is enabledKhairul Anuar Romli
Enabling runtime PM allows the kernel to gate clocks and power to idle devices. On SoCFPGA, a warm reset does not fully reinitialize these domains.This leaves devices suspended and powered down, preventing U-Boot or the kernel from reusing them after a warm reset, which breaks the boot process. Fixes: 4892b374c9b7 ("mtd: spi-nor: cadence-quadspi: Add runtime PM support") CC: stable@vger.kernel.org # 6.12+ Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Niravkumar L Rabara <nirav.rabara@altera.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com> Link: https://patch.msgid.link/910aad68ba5d948919a7b90fa85a2fadb687229b.1757491372.git.khairul.anuar.romli@altera.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-17spi: geni-qcom: Load spi qup Firmware from linux sideViken Dadhaniya
Add provision to load firmware of Serial engine for SPI protocol from Linux Execution Environment on running on APPS processor. Co-developed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> Signed-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20250911043256.3523057-6-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-17spi: mt65xx: add dual and quad mode for standard spi deviceTim Kuo
Mediatek SPI hardware natively supports dual and quad modes, and these modes are already enabled for SPI flash devices under spi-mem framework in MTK SPI controller spi-mt65xx. However, other SPI devices, such as touch panels, are limited to single mode because spi-mt65xx lacks SPI mode argument parsing from SPI framework for these SPI devices outside spi-mem framework. This patch adds dual and quad mode support for these SPI devices by introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing. Signed-off-by: Tim Kuo <Tim.Kuo@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20250917055839.500615-1-Tim.Kuo@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-16Miscellaneous fixes and clean-upsMark Brown
Merge series from Santhosh Kumar K <s-k6@ti.com>: This series introduces some small but important fixes and cleanups in the Cadence QSPI Controller. Tested on TI's AM62A SK and AM62P SK: Logs: https://gist.github.com/santhosh21/0d25767b58d9a1d9624f2c502dd8f36b
2025-09-15Merge tag 'microchip-soc-6.18' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers Microchip ARM64 SoC updates for v6.18: This update includes: - basic infrastructure support for Microchip LAN969x SoC - SoC ARCH symbols (existing SparX-5, new LAN969x) under the ARCH_MICROCHIP hidden symbol (already in use by AT91 in 6.17) - addition of that new symbol for drivers that are shared by Microchip SoC-s now and in the future * tag 'microchip-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: crypto: atmel-aes: make it selectable for ARCH_MICROCHIP char: hw_random: atmel: make it selectable for ARCH_MICROCHIP i2c: at91: make it selectable for ARCH_MICROCHIP spi: atmel: make it selectable for ARCH_MICROCHIP tty: serial: atmel: make it selectable for ARCH_MICROCHIP mfd: at91-usart: Make it selectable for ARCH_MICROCHIP arm64: lan969x: Add support for Microchip LAN969x SoC arm64: Add config for Microchip SoC platforms Link: https://lore.kernel.org/r/20250915123548.13722-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15spi: amlogic: Fix error checking on regmap_write callColin Ian King
Currently a call to regmap_write is not being error checked because the return checke is being performed on the variable ret and this variable is not assigned the return value from the regmap_write call. Fix this by adding in the missing assignment. Fixes: 4670db6f32e9 ("spi: amlogic: add driver for Amlogic SPI Flash Controller") Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://patch.msgid.link/20250913201612.1338217-1-colin.i.king@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-14spi: apple: Add "apple,t8103-spi" compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,spi" anymore [1]. Use "apple,t8103-spi" as base compatible as it is the SoC the driver and bindings were written for. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-12spi: axi-spi-engine: improve version checksMark Brown
Merge series from David Lechner <dlechner@baylibre.com>: We have a pending major version bump for the axi-spi-engine so to prepare for that, improve the existing version checks for feature enablement.
2025-09-12support for Amlogic SPI Flash Controller IPMark Brown
Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>: This Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community (drivers/mtd/nand/raw/meson_nand.c). This submission supports the SPI mode. Add the drivers and bindings corresponding to the SPI Flash Controller.
2025-09-11spi: axi-spi-engine: use adi_axi_pcore_ver_gteq()David Lechner
Make use of the adi_axi_pcore_ver_gteq() helper to make version checks more readable and robust against a major version bump. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20250815-spi-axi-spi-enigne-improve-version-checks-v1-2-13bde357d5b6@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-10spi: amlogic: add driver for Amlogic SPI Flash ControllerFeng Chen
This driver provides support for the SPI mode of the Amlogic Flash Controller. It supports both SPI NOR flash and SPI NAND flash. For SPI NAND, the Host ECC hardware engine can be enabled. The controller implements the SPI-MEM interface and does not support generic SPI. Signed-off-by: Feng Chen <feng.chen@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20250910-spifc-v6-2-1574aa9baebd@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Use BIT() macros where possibleVignesh Raghavendra
Convert few open coded bit shifts to BIT() macro for better readability. No functional changes intended. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-5-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Fix cqspi_setup_flash()Santhosh Kumar K
The 'max_cs' stores the largest chip select number. It should only be updated when the current 'cs' is greater than existing 'max_cs'. So, fix the condition accordingly. Also, return failure if there are no flash device declared. Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-select") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-4-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Flush posted register writes before DAC accessPratyush Yadav
cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-3-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Flush posted register writes before INDAC accessPratyush Yadav
cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-2-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: atmel: make it selectable for ARCH_MICROCHIPRobert Marko
LAN969x uses the Atmel SPI, so make it selectable for ARCH_MICROCHIP to avoid needing to update depends in future if other Microchip SoC-s use it as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2025-09-08spi: s3c64xx: Drop S3C2443Krzysztof Kozlowski
Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles or platform data ID. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Message-ID: <20250830132605.311115-3-krzysztof.kozlowski@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Target mode improvementsMark Brown
Merge series from James Clark <james.clark@linaro.org>: Improve usability of target mode by reporting FIFO errors and increasing the buffer size when DMA is used. While we're touching DMA stuff also switch to non-coherent memory, although this is unrelated to target mode. With the combination of the commit to increase the DMA buffer size and the commit to use non-coherent memory, the host mode performance figures are as follows on S32G3: # spidev_test --device /dev/spidev1.0 --bpw 8 --size <test_size> --cpha --iter 10000000 --speed 10000000 Coherent (4096 byte transfers): 6534 kbps Non-coherent: 7347 kbps Coherent (16 byte transfers): 447 kbps Non-coherent: 448 kbps Just for comparison running the same test in XSPI mode: 4096 byte transfers: 2143 kbps 16 byte transfers: 637 kbps These tests required hacking S32G3 to use DMA in host mode, although the figures should be representative of target mode too where DMA is used. And the other devices that use DMA in host mode should see similar improvements.
2025-09-03spi: spi-qpic-snand: unregister ECC engine on probe error and device removeGabor Juhos
The on-host hardware ECC engine remains registered both when the spi_register_controller() function returns with an error and also on device removal. Change the qcom_spi_probe() function to unregister the engine on the error path, and add the missing unregistering call to qcom_spi_remove() to avoid possible use-after-free issues. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Message-ID: <20250903-qpic-snand-unregister-ecceng-v1-1-ef5387b0abdc@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Report FIFO overflows as errorsJames Clark
In target mode, the host sending more data than can be consumed would be a common problem for any message exceeding the FIFO or DMA buffer size. Cancel the whole message as soon as this condition is hit as the message will be corrupted. Only do this for target mode in a DMA transfer, it's not likely these flags will be set in host mode so it's not worth adding extra checks. In IRQ and polling modes we use the same transfer functions for hosts and targets so the error flags always get checked. This is slightly inconsistent but it's not worth doing the check conditionally because it may catch some host programming errors in the future. Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-7-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Increase target mode DMA buffer sizeJames Clark
When the device is configured as a target, the host won't stop sending data while we're draining the buffer which leads to FIFO underflows and corruption. Increase the DMA buffer size to the maximum words that edma can transfer once to reduce the chance of this happening. In host mode, the driver is able to split up a transfer into smaller chunks so we don't need to increase the size. While in target mode, the length of the transfer is determined by the remote host and can be larger than whatever default buffer size we pick. Keeping the buffer small in host mode avoids wasting memory, but allocating the largest possible in target mode gives the lowest possible chance of dropping any data from the host. While we could allocate per-transfer using the exact size of the transfer, 128K is quite a large allocation and there is a chance it could fail due to memory fragmentation unless it's allocated once at init time. Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-6-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Use whole page for DMA buffersJames Clark
dma_alloc_noncoherent() allocations are backed by a full page anyway, so use it all. VF610 devices used to use the full page before commit a957499bd437 ("spi: spi-fsl-dspi: Fix bits-per-word acceleration in DMA mode"), but others still used the FIFO size. After that commit, all devices used the FIFO size. Now all devices use the full page. Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-5-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Use non-coherent memory for DMAJames Clark
Using coherent memory here isn't functionally necessary, we're only either sending data to the device or reading from it. This means explicit synchronizations are only required around those points and the change is fairly trivial. This gives us around a 10% increase in throughput for large DMA transfers and no loss for small transfers. Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-4-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: spi-fsl-dspi: Stub out DMA functionsJames Clark
In a later commit we'll use dma_alloc_noncoherent() which isn't stubbed out for builds without CONFIG_DMA_ENGINE and results in the following build error: spi-fsl-dspi.c:(.text+0x644): undefined reference to `dma_free_pages' m68k-linux-ld: spi-fsl-dspi.c:(.text+0x67a): undefined reference to `dma_free_pages' To continue to support devices that only need XSPI mode and so that randconfig builds work, stub out DMA functionality in the DSPI driver. Although older parts of the DMA API have their own stubs, it's intentional that newer parts don't follow the same pattern. Therefore individual drivers should not compile in calls unless CONFIG_DMA_ENGINE is set. Link: https://lore.kernel.org/oe-kbuild-all/202506160036.t9VDxF6p-lkp@intel.com/ Signed-off-by: James Clark <james.clark@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-3-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: fsl-dspi: Store status directly in cur_msg->statusJames Clark
This will allow us to return a status from the interrupt handler in a later commit and avoids copying it at the end of dspi_transfer_one_message(). For consistency make polling and DMA modes use the same mechanism. No functional changes intended. Signed-off-by: James Clark <james.clark@linaro.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-2-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: fsl-dspi: Avoid using -EINPROGRESS error codeJames Clark
Refactor dspi_rxtx() and dspi_poll() to not return -EINPROGRESS because this isn't actually a status that is ever returned to the core layer but some internal state. Use true/false return value on dspi_rxtx() for this instead. This will help separate internal vs external status for the later change to store the external status directly in cur_msg->status. No functional changes intended. Co-developed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-ID: <20250902-james-nxp-spi-dma-v6-1-f7aa2c5e56e2@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-03spi: mxs: fix "transfered"->"transferred"Xichao Zhao
Trivial fix to spelling mistake in comment text. Signed-off-by: Xichao Zhao <zhao.xichao@vivo.com> Message-ID: <20250903020347.563003-1-zhao.xichao@vivo.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Generic fixes and support forMark Brown
Merge series from James Clark <james.clark@linaro.org>: Various fixes for LPSI along with some refactorings. None of the fixes are strictly related to S32G, however these changes all originate from the work to support S32G devices. The only commits that are strictly related are for the new s32g2 and s32g3 compatible strings.
2025-09-01spi: cadence-quadspi: Implement refcount to handle unbind during busyKhairul Anuar Romli
driver support indirect read and indirect write operation with assumption no force device removal(unbind) operation. However force device removal(removal) is still available to root superuser. Unbinding driver during operation causes kernel crash. This changes ensure driver able to handle such operation for indirect read and indirect write by implementing refcount to track attached devices to the controller and gracefully wait and until attached devices remove operation completed before proceed with removal operation. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com> Reviewed-by: Niravkumar L Rabara <nirav.rabara@altera.com> Link: https://patch.msgid.link/8704fd6bd2ff4d37bba4a0eacf5eba3ba001079e.1756168074.git.khairul.anuar.romli@altera.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Add compatible for S32GLarisa Grigore
S32G doesn't have the max prescale erratum (default) and it can query the max number of CS from hardware, so add those settings. Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-9-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Parameterize reading num-cs from hardwareJames Clark
Add query_hw_for_num_cs in devtype to avoid directly checking compatible string "fsl,imx93-spi". No functionality change. Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-8-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratumJames Clark
This erratum only ever results in a max value of 1, otherwise the full 3 bits are available. To avoid repeating the same default prescale value for every new device's devdata, treat 0 as no limit (7) and only set a value when the erratum is present. Change the field to be 3 bits to catch out of range definitions. No functionality change. Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-7-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Constify devtype datasJames Clark
Add const for all devtype_data. Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-6-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Clear status register after disabling the moduleLarisa Grigore
Clear the error flags after disabling the module to avoid the case when a flag is set again between flag clear and module disable. And use SR_CLEAR_MASK to replace hardcoded value for improved readability. Although fsl_lpspi_reset() was only introduced in commit a15dc3d657fa ("spi: lpspi: Fix CLK pin becomes low before one transfer"), the original driver only reset SR in the interrupt handler, making it vulnerable to the same issue. Therefore the fixes commit is set at the introduction of the driver. Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-4-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Reset FIFO and disable module on transfer abortLarisa Grigore
In DMA mode fsl_lpspi_reset() is always called at the end, even when the transfer is aborted. In PIO mode aborts skip the reset leaving the FIFO filled and the module enabled. Fix it by always calling fsl_lpspi_reset(). Fixes: a15dc3d657fa ("spi: lpspi: Fix CLK pin becomes low before one transfer") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-3-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Set correct chip-select polarity bitLarisa Grigore
The driver currently supports multiple chip-selects, but only sets the polarity for the first one (CS 0). Fix it by setting the PCSPOL bit for the desired chip-select. Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-2-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-01spi: spi-fsl-lpspi: Fix transmissions when using CONTLarisa Grigore
Commit 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use CONT") breaks transmissions when CONT is used. The TDIE interrupt should not be disabled in all cases. If CONT is used and the TX transfer is not yet completed yet, but the interrupt handler is called because there are characters to be received, TDIE is replaced with FCIE. When the transfer is finally completed, SR_TDF is set but the interrupt handler isn't called again. Fixes: 6a130448498c ("spi: lpspi: Fix wrong transmission when don't use CONT") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-1-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-29spi: microchip-core-qspi: stop checking viability of op->max_freq in ↵Conor Dooley
supports_op callback In commit 13529647743d9 ("spi: microchip-core-qspi: Support per spi-mem operation frequency switches") the logic for checking the viability of op->max_freq in mchp_coreqspi_setup_clock() was copied into mchp_coreqspi_supports_op(). Unfortunately, op->max_freq is not valid when this function is called during probe but is instead zero. Accordingly, baud_rate_val is calculated to be INT_MAX due to division by zero, causing probe of the attached memory device to fail. Seemingly spi-microchip-core-qspi was the only driver that had such a modification made to its supports_op callback when the per_op_freq capability was added, so just remove it to restore prior functionality. CC: stable@vger.kernel.org Reported-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Fixes: 13529647743d9 ("spi: microchip-core-qspi: Support per spi-mem operation frequency switches") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-ID: <20250825-during-ploy-939bdd068593@spud> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-28add COMPILE_TEST supportMark Brown
Merge series from Rosen Penev <rosenp@gmail.com>: Allows the buildbots to test compilation. The driver has nothing architecture specific.
2025-08-28spi: Drop dev_pm_domain_detach() callClaudiu Beznea
Starting with commit f99508074e78 ("PM: domains: Detach on device_unbind_cleanup()"), there is no longer a need to call dev_pm_domain_detach() in the bus remove function. The device_unbind_cleanup() function now handles this to avoid invoking devres cleanup handlers while the PM domain is powered off, which could otherwise lead to failures as described in the above-mentioned commit. Drop the explicit dev_pm_domain_detach() call and rely instead on the flags passed to dev_pm_domain_attach() to power off the domain. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Message-ID: <20250827101612.928008-1-claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-28spi: rb4xx: use devm for clk_prepare_enableRosen Penev
Remove the remove function as it no longer does anything useful. Also remove platform_set_drvdata as get becomes completely unused. Signed-off-by: Rosen Penev <rosenp@gmail.com> Message-ID: <20250826212413.15065-4-rosenp@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-28spi: rb4xx: add COMPILE_TEST supportRosen Penev
Copy macros from ath79 SPI driver to allow compilation on all platforms and remove ath79 specific header. Signed-off-by: Rosen Penev <rosenp@gmail.com> Message-ID: <20250826212413.15065-3-rosenp@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-28spi: rb4xx: depend on OFRosen Penev
There's no support for non OF platforms. Better to depend on OF explicitly. Also fixes a warning/error about the dt table being unused because of of_match_ptr on non OF platforms. Signed-off-by: Rosen Penev <rosenp@gmail.com> Message-ID: <20250826212413.15065-2-rosenp@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-08-21Merge tag 'spi-fix-v6.17-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small collection of fixes that came in during the past week, a few driver specifics plus one fix for the spi-mem core where we weren't taking account of the frequency capabilities of the system when determining if it can support an operation" * tag 'spi-fix-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: st: fix PM macros to use CONFIG_PM instead of CONFIG_PM_SLEEP spi: spi-qpic-snand: fix calculating of ECC OOB regions' properties spi: spi-fsl-lpspi: Clamp too high speed_hz spi: spi-mem: add spi_mem_adjust_op_freq() in spi_mem_supports_op() spi: spi-mem: Add missing kdoc argument spi: spi-qpic-snand: use correct CW_PER_PAGE value for OOB write
2025-08-21spi: st: fix PM macros to use CONFIG_PM instead of CONFIG_PM_SLEEPRaphael Gallais-Pou
pm_sleep_ptr() depends on CONFIG_PM_SLEEP while pm_ptr() depends on CONFIG_PM. Since ST SSC4 implements runtime PM it makes sense using pm_ptr() here. For the same reason replace PM macros that use CONFIG_PM. Doing so prevents from using __maybe_unused attribute of runtime PM functions. Link: https://lore.kernel.org/lkml/CAMuHMdX9nkROkAJJ5odv4qOWe0bFTmaFs=Rfxsfuc9+DT-bsEQ@mail.gmail.com Fixes: 6f8584a4826f ("spi: st: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()") Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250820180310.9605-1-rgallaispou@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-20 01:08:28 +0000