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There is a spelling mistake in a dev_warn message. Fix it.
Signed-off-by: Colin Ian King <coking@nvidia.com>
Link: https://patch.msgid.link/20251016153000.9142-1-coking@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Attaching UBI on the flash with more than one plane per lun will lead to
the following error:
[ 2.980989] spi-nand spi0.0: Micron SPI NAND was found.
[ 2.986309] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[ 2.994978] 2 fixed-partitions partitions found on MTD device spi0.0
[ 3.001350] Creating 2 MTD partitions on "spi0.0":
[ 3.006159] 0x000000000000-0x000000020000 : "bl2"
[ 3.011663] 0x000000020000-0x000010000000 : "ubi"
...
[ 6.391748] ubi0: attaching mtd1
[ 6.412545] ubi0 error: ubi_attach: PEB 0 contains corrupted VID header, and the data does not contain all 0xFF
[ 6.422677] ubi0 error: ubi_attach: this may be a non-UBI PEB or a severe VID header corruption which requires manual inspection
[ 6.434249] Volume identifier header dump:
[ 6.438349] magic 55424923
[ 6.441482] version 1
[ 6.444007] vol_type 0
[ 6.446539] copy_flag 0
[ 6.449068] compat 0
[ 6.451594] vol_id 0
[ 6.454120] lnum 1
[ 6.456651] data_size 4096
[ 6.459442] used_ebs 1061644134
[ 6.462748] data_pad 0
[ 6.465274] sqnum 0
[ 6.467805] hdr_crc 61169820
[ 6.470943] Volume identifier header hexdump:
[ 6.475308] hexdump of PEB 0 offset 4096, length 126976
[ 6.507391] ubi0 warning: ubi_attach: valid VID header but corrupted EC header at PEB 4
[ 6.515415] ubi0 error: ubi_compare_lebs: unsupported on-flash UBI format
[ 6.522222] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
[ 6.529294] UBI error: cannot attach mtd1
Non dirmap reading works good. Looking to spi_mem_no_dirmap_read() code we'll see:
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
struct spi_mem_op op = desc->info.op_tmpl;
int ret;
// --- see here ---
op.addr.val = desc->info.offset + offs;
//-----------------
op.data.buf.in = buf;
op.data.nbytes = len;
ret = spi_mem_adjust_op_size(desc->mem, &op);
if (ret)
return ret;
ret = spi_mem_exec_op(desc->mem, &op);
if (ret)
return ret;
return op.data.nbytes;
}
The similar happens for spi_mem_no_dirmap_write(). Thus the address
passed to the flash should take in the account the value of
desc->info.offset.
This patch fix dirmap reading/writing of flashes with more than one
plane per lun.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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Current dirmap code does not switch back to non-dma mode in the case of
error. This is wrong.
This patch fixes dirmap read/write error path.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-6-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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Booting without this patch and disabled dirmap support results in
[ 2.980719] spi-nand spi0.0: Micron SPI NAND was found.
[ 2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[ 2.994709] 2 fixed-partitions partitions found on MTD device spi0.0
[ 3.001075] Creating 2 MTD partitions on "spi0.0":
[ 3.005862] 0x000000000000-0x000000020000 : "bl2"
[ 3.011272] 0x000000020000-0x000010000000 : "ubi"
...
[ 6.195594] ubi0: attaching mtd1
[ 13.338398] ubi0: scanning is finished
[ 13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found
[ 13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
[ 13.356897] UBI error: cannot attach mtd1
If dirmap is disabled or not supported in the spi driver, the dirmap requests
will be executed via exec_op() handler. Thus, if the hardware supports
dual/quad spi modes, then corresponding requests will be sent to exec_op()
handler. Current driver does not support such requests, so error is arrised.
As result the flash can't be read/write.
This patch adds support of dual and quad wires spi modes to exec_op() handler.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-4-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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This driver can accelerate single page operations only, thus
continuous reading mode should not be used.
Continuous reading will use sizes up to the size of one erase block.
This size is much larger than the size of single flash page. Use this
difference to identify continuous reading and return an error.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Link: https://patch.msgid.link/20251012121707.2296160-2-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Haibo Chen <haibo.chen@nxp.com>:
PATCH 1: different operations maybe require different max frequency, so
add flexspi to handle such case, re-config the clock rate when
new coming operation require new clock frequency.
Patch 2: add workaround for erratum ERR050272. Since only add 4us dealy
in nxp_fspi_dll_calibration(), so do not distinguish different
platforms.
Patch 3: add max frequency limitation for different sample clock source
selection. Datasheet give max 66MHz for mode 0 and 166MHz for
mode 3. And IC suggest to add this limitation on all SoCs for
safety and stability.
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There is an error building when
Compiler version: gcc (GCC) 14.3.0
Assembler version: GNU assembler (GNU Binutils) 2.44
"
Error log:
WARNING: modpost: missing MODULE_DESCRIPTION() in arch/arm/probes/kprobes/test-kprobes.o
ERROR: modpost: "__ffsdi2" [drivers/spi/spi-amlogic-spifc-a4.ko] undefined!
"
Use __ffs API instead of __bf_shf to be safer.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Closes: https://lore.kernel.org/all/f594c621-f9e1-49f2-af31-23fbcb176058@roeck-us.net/
Fixes: 4670db6f32e9 ("spi: amlogic: add driver for Amlogic SPI Flash Controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://patch.msgid.link/20251015-fix-spifc-a4-v1-1-08e0900e5b7e@amlogic.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Benoît Monin <benoit.monin@bootlin.com>:
The DesignWare SPI controller can act as a host or a target; the
choice between the two is set in hardware and cannot be changed by
software. When configured in target mode, the controller has a much
reduced set of capabilities. It only has a single chip-select input and
can only run standard SPI mode (no dual, quad, or octal mode). Despite
this, the overall logic of doing an SPI transfer and the register layout
is identical between both modes, so implementing the target mode reuses
much of the existing code.
The first part of this two-patch series renames the spi_controller to
ctlr instead of host and also changes the suffix of the related functions
to controller. This is done to avoid confusion when referring to the
controller in target mode.
The second patch implements the target mode support by allocating an
SPI controller of the correct type based on the spi-slave property. The
controller is then configured differently depending on the mode. For
an SPI transfer, the same transfer_one() callback is used, with the
difference being in dw_spi_update_config() where only the CTRLR0
register is set. The other registers are not relevant in target mode
and are read-only.
I am posting this as an RFC because I could only perform partial testing
on my setup. I am using an SoC with two DesignWare SPI memory-mapped
controllers identified as Synopsys DWC APB SSI v4.03, one in host mode and
the other in target mode. On the evaluation board, a microcontroller acts
as an SPI relay between the two, but it has some limitations. The number
of bits per word is fixed, as are the clock phase and polarity. It also
only copies data from the host to the target. With this limited setup,
I did test that data can be successfully transferred from the host
to the target using spidev_test. I also checked that polling works by
temporarily disabling the IRQ, but I cannot test DMA. Therefore, more
testing on different devices would be welcome.
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Merge series from Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>:
This patch series introduces several improvements to the
ASPEED SPI driver, targeting better stability, compatibility
and, flexibility across multiple ASPEED platforms.
Key changes include:
* Clock selection strategy update
Improves fallback logic when timing calibration is skipped or
fails, ensuring reliable boot behavior.
* Timing calibration enhancement for AST2600
Replaces the previous "first-pass" strategy with a more robust
algorithm that selects the optimal timing point.
* Default address decoding assignment
Ensures each chip select (CS) has a valid decoding range during
probe, avoiding detection failures due to missing or incorrect
bootloader setup.
* Centralized address decoding management
Refactors the decoding logic to centrally assign address windows,
preventing improper trimming and improving layout flexibility.
* Per-platform decoding adjustment
Introduces platform-specific `adjust_window` callbacks to handle
platform specific hardware constraints for address decoding range.
* Selective memory mapping
Optimizes memory usage by mapping only the required address window
per CS to avoid exhaustion.
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In csqspi_probe(), when cqspi_request_mmap_dma() returns -EPROBE_DEFER,
we handle the error by jumping to probe_setup_failed.
In that label, we call pm_runtime_disable(), even if we never called
pm_runtime_enable() before.
Because of this, the driver cannot probe:
[ 2.690018] cadence-qspi 47040000.spi: No Rx DMA available
[ 2.699735] spi-nor spi0.0: resume failed with -13
[ 2.699741] spi-nor: probe of spi0.0 failed with error -13
Only call pm_runtime_disable() if it was enabled by adding a new
label to handle cqspi_request_mmap_dma() failures.
Fixes: b07f349d1864 ("spi: spi-cadence-quadspi: Fix pm runtime unbalance")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://patch.msgid.link/20251009-cadence-quadspi-fix-pm-runtime-v2-1-8bdfefc43902@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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selection
For different sample clock source selection, the max frequency
flexspi supported are different. For mode 0, max frequency is 66MHz.
For mode 3, the max frequency is 166MHz.
Refer to 3.9.9 FlexSPI timing parameters on page 65.
https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf
Though flexspi maybe still work under higher frequency, but can't
guarantee the stability. IC suggest to add this limitation on all
SoCs which contain flexspi.
Fixes: c07f27032317 ("spi: spi-nxp-fspi: add the support for sample data from DQS pad")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20250922-fspi-fix-v1-3-ff4315359d31@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Due to the erratum ERR050272, the DLL lock status register STS2
[xREFLOCK, xSLVLOCK] bit may indicate DLL is locked before DLL is
actually locked. Add an extra 4us delay as a workaround.
refer to ERR050272, on Page 20.
https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf
Fixes: 99d822b3adc4 ("spi: spi-nxp-fspi: use DLL calibration when clock rate > 100MHz")
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20250922-fspi-fix-v1-2-ff4315359d31@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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rate
Current operation contain the max_freq, so new coming operation may use
new clock rate, need to re-config the clock rate to match the requirement.
Fixes: 26851cf65ffc ("spi: nxp-fspi: Support per spi-mem operation frequency switches")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20250922-fspi-fix-v1-1-ff4315359d31@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Ensure my CI has a sensible baseline.
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Add an offset parameter that can be passed in the periodic trigger.
This is useful for example when ADC drivers implement a separate periodic
signal to trigger conversion and need offload to read the result with
some delay. While at it, add some documentation to offload periodic trigger
parameters.
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Link: https://patch.msgid.link/cd315e95c0bd8523f00e91c400abcd6a418e5924.1759760519.git.marcelo.schmitt@analog.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Previously, the driver mapped the entire SPI address decoding region during
probe. On systems with small flash or limited memory, this could lead to
excessive memory usage or allocation failures.
This patch changes the strategy to initially map a small address window
for SPI flash device probing. After determining each chip select's flash
size, the driver unmaps the temporary region and remaps only the required
address window accordingly.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-7-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Different ASPEED SoCs have specific limitations on SPI address decoding,
such as total range size, minimum window size per CS, and alignment
requirements. The original adjustment logic only handles simple cases
and could fail in more complex setups found in advanced board designs,
e.g., small flash on CS0 and large flash on CS1, or when the total physical
flash size exceeds the decoding range supported by the SPI controller.
This patch introduces a per-platform adjust_window callback to handle
these constraints properly. Each platform defines its own logic to
adjust decoding ranges, trim excess size, and ensure alignment.
If trimming is required, the affected CS will fall back to user mode
access to ensure the entire flash remains accessible from the MTD layer.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-6-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The original approach to handling address decoding overlaps was to trim
the next region directly. If the next CS's decoding range was fully
overlapped by the current one, it would be forcibly closed by trimming
its size to zero. This could lead expected behavior, especially on
the platform with multiple flashes layout.
To solve improper trimming problem, this patch collects the required
address decoding size at each stage, then, (re-)arragne address decoding
region to each CS centrally with knowing the total AHB decoding size.
If a segment register cannot be updated (e.g. due to bootloader write
protection), the original value is kept to avoid breaking access and
an error is reported if the total decoding size of all CS exceeds
the total AHB decoding size.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-5-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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On some platforms, we cannot assume that the whole address decoding range
value is ready for each CS. Especially for chip selects other than CS0,
the address decoding range may not be properly configured before the kernel
stage, or the existing configuration may be unsuitable. This can lead to
SPI flash detection failures during driver probe.
To ensure reliable initialization, this patch forcibly assigns a default
address decoding range to each chip select based on a platform-specific
minimum window size. Unused chip selects are explicitly disabled to avoid
conflicts.
This change improves robustness across platforms with varying bootloader
behavior and ensures consistent SPI flash initialization.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-4-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Starting with the AST2600 platform, most platfom manufacturers have
adopted more complex board designs and signal routing, making SPI
timing calibration increasingly sensitive and critical. Previously,
the driver selected the first "PASS" timing point during calibration,
which may not yield the most stable result.
This patch introduces a more robust calibration method:
- It evaluates all combinations of HCLK sample point delay and DI input
delay. The results are stored in a 2D buffer for further comparison.
- Because the timing delay behavior is non-linear across HCLK sample
points, the optimal timing point is selected as the center of the
longest consecutive "PASS" interval within a single HCLK sample
point row.
This approach ensures better stability and precision in SPI read timing,
especially under complex signal integrity conditions.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-3-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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This patch updates the SPI clock selection logic for cases where
timing calibration is not performed or the results are failed.
Timing calibration process is skipped in the two scenarios below.
- Low-entropy data in the calibration region:
The driver skips timing calibration if the data read from the
SPI flash contains mostly 0x00 or 0xFF. Originally, the driver
used a low-frequency clock to read this region as golden data.
However, due to variations in host characteristics and image
layout, we cannot assume sufficient entropy in this region to
ensure reliable calibration.
- Low-speed configurations (< 40MHz):
The ASPEED SPI controller does not support timing calibration when
the max_speed_hz of the SPI device is below 40MHz.
In both cases, the SPI clock frequency specified in the device tree
should be used directly. When timing calibration is skipped, it is
the board vendor's responsibility to ensure that the SPI flash
SI (Signal Integrity) is sufficient for reliable operation at the
configured frequency.
When timing calibration processes is execued and all potential clock
frequencies are performed, but are all failed, the lower clock frequency
should be adopted to ensure the overall system can boot up successfully.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251001112605.1130723-2-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Implement target mode for the DesignWare controller with the following
changes:
Allocate an SPI controller of the correct type based on the spi-slave
property in dw_spi_add_controller() and set the controller properties
depending on its type. Since they are only relevant when acting as a host
controller, settings related to chip-select control and the set_cs()
callback are only set in host mode, as are the loopback support, the
memory operations and the maximum frequency. The target_abort() callback
is set only when configured in target mode.
The number of chip-select is set to 1 in dw_spi_hw_init() since the
controller only has one CS input in target mode.
In dw_spi_update_config(), return after setting the CTRLR0 register as
the other registers are only relevant in host mode and are read-only
in target mode. This function is called as part of the transfer_one()
callback, which is identical in both the host and target mode.
Move the code implementing the handle_err() callback to a new function
named dw_spi_abort(), and use it to implement both the handle_err()
and the target_abort() callbacks.
Finally, drop the error path on the spi-slave property in
dw_spi_mmio_probe(), as it is now a valid configuration.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Link: https://patch.msgid.link/20251002-spi-dw-target-v1-2-993e91c1a712@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Since the designware SPI controller can act as both a target and a host,
rename spi_controller member of the dw_spi struct to ctlr instead of host.
Similarly, rename the functions handling the controller, using controller
instead of host as the suffix.
No functional changes intended.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Link: https://patch.msgid.link/20251002-spi-dw-target-v1-1-993e91c1a712@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Currently reset_control_deassert() is called without checking its
return value. This can lead to silent failures when reset deassertion
fails.
Add proper error handling to:
1. Check the return value of reset_control_deassert()
2. Return the error to the caller
3. Provide meaningful error message using dev_err_probe()
This ensures that reset-related failures are properly reported during
probe and helps with debugging reset issues.
Signed-off-by: Artem Shimko <a.shimko.dev@gmail.com>
Link: https://patch.msgid.link/20251007101134.1912895-1-a.shimko.dev@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Use DMA-API dma_map_single() call for getting the DMA address of the
transfer buffer instead of hacking with virt_to_phys().
This fixes the following DMA-API debug warning:
------------[ cut here ]------------
DMA-API: rockchip-sfc fe300000.spi: device driver tries to sync DMA memory it has not allocated [device address=0x000000000cf70000] [size=288 bytes]
WARNING: kernel/dma/debug.c:1106 at check_sync+0x1d8/0x690, CPU#2: systemd-udevd/151
Modules linked in: ...
Hardware name: Hardkernel ODROID-M1 (DT)
pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : check_sync+0x1d8/0x690
lr : check_sync+0x1d8/0x690
..
Call trace:
check_sync+0x1d8/0x690 (P)
debug_dma_sync_single_for_cpu+0x84/0x8c
__dma_sync_single_for_cpu+0x88/0x234
rockchip_sfc_exec_mem_op+0x4a0/0x798 [spi_rockchip_sfc]
spi_mem_exec_op+0x408/0x498
spi_nor_read_data+0x170/0x184
spi_nor_read_sfdp+0x74/0xe4
spi_nor_parse_sfdp+0x120/0x11f0
spi_nor_sfdp_init_params_deprecated+0x3c/0x8c
spi_nor_scan+0x690/0xf88
spi_nor_probe+0xe4/0x304
spi_mem_probe+0x6c/0xa8
spi_probe+0x94/0xd4
really_probe+0xbc/0x298
...
Fixes: b69386fcbc60 ("spi: rockchip-sfc: Using normal memory for dma")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://patch.msgid.link/20251003114239.431114-1-m.szyprowski@samsung.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"There's one big core change in this release, Jonas Gorski has
addressed the issues with multiple chip selects which makes things
more robust and stable. Otherwise there's quite a bit of driver work,
as well as some new drivers several existing drivers have had quite a
bit of work done on them.
Possibly the most interesting thing is the VirtIO driver, this is
apparently useful for some automotive applications which want to keep
as small and robust a host system as they can, moving less critical
functionality into guests.
- James Clark has done some substantial updates on the Freescale DSPI
driver, porting in code from the BSP and building onm top of that
to fix some bugs and increase performance
- Jonas Gorski has fixed the issues with handling multple chip
selects, making things more robust and scalable
- Support for higher performance modes in the NXP FSPI driver from
Haibo Chen
- Removal of the obsolete S3C2443 driver, the underlying SoC support
has been removed from the kernel
- Support for Amlogic AL113L2, Atmel SAMA7D65 and SAM9x7 and for
VirtIO controllers"
* tag 'spi-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (74 commits)
spi: ljca: Remove Wentong's e-mail address
spi: rename SPI_CS_CNT_MAX => SPI_DEVICE_CS_CNT_MAX
spi: reduce device chip select limit again
spi: don't check spi_controller::num_chipselect when parsing a dt device
spi: drop check for validity of device chip selects
spi: move unused device CS initialization to __spi_add_device()
spi: keep track of number of chipselects in spi_device
spi: fix return code when spi device has too many chipselects
SPI: Add virtio SPI driver
virtio-spi: Add virtio-spi.h
virtio: Add ID for virtio SPI
spi: rpc-if: Add resume support for RZ/G3E
spi: rpc-if: Drop deprecated SIMPLE_DEV_PM_OPS
spi: spi-qpic-snand: simplify clock handling by using devm_clk_get_enabled()
spi: spi-nxp-fspi: Add OCT-DTR mode support
spi: spi-nxp-fspi: add the support for sample data from DQS pad
spi: spi-nxp-fspi: Add the DDR LUT command support
spi: spi-nxp-fspi: set back to dll override mode when clock rate < 100MHz
spi: spi-nxp-fspi: extract function nxp_fspi_dll_override()
spi: atmel-quadspi: Add support for sama7d65 QSPI
...
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https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers
Apple SoC driver updates for 6.18
Krzysztof Kozlowski asked us to move away from generic compatibles:
- Adjust all dt-bindings to use apple,t8103-XXXX instead of apple,XXXX
as fallback and add a comment that the old generic list should no
longer be extended.
- Add new fallback compatibles to pinctrl, pmdomain, spi, and mca
drivers. These changes have been Acked by their subsystem maintainers
to be merged through our tree together with the dt-bindings.
Support for pre-M1 Apple Silicon:
- SART and mailbox gain support for Apple's A11, which are both
required for NVMe.
- NVMe also gains support for Apple's A11 and the nvme maintainers
prefer that we merge this through the soc tree together with
the mailbox and SART changes.
- SPMI compatibles for A11 and T2 have been added, also going through
the soc tree due to conflicts with the generic compatible removal and
because no driver change is required.
Signed-off-by: Sven Peter <sven@kernel.org>
* tag 'apple-soc-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (32 commits)
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
spi: apple: Add "apple,t8103-spi" compatible
ASoC: apple: mca: Add "apple,t8103-mca" compatible
pinctrl: apple: Add "apple,t8103-pinctrl" as compatible
spi: dt-bindings: apple,spi: Add t6020-spi compatible
ASoC: dt-bindings: apple,mca: Add t6020-mca compatible
dt-bindings: dma: apple,admac: Add t6020-admac compatible
dt-bindings: clock: apple,nco: Add t6020-nco compatible
dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatible
dt-bindings: spmi: apple,spmi: Add t6020-spmi compatible
dt-bindings: mfd: apple,smc: Add t6020-smc compatible
dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatible
dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatible
dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatible
dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatible
dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatibles
dt-bindings: mailbox: apple,mailbox: Add t6020 compatible
dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatible
dt-bindings: iommu: dart: Add apple,t6020-dart compatible
...
Link: https://lore.kernel.org/r/20250920123028.49973-1-sven@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
More Qualcomm device driver updates for v6.18
Introduce support for loading firmware into the QUP serial engines from
Linux, which allows deferring selection of which protocol (uart, i2c,
spi, etc) a given SE should have until the OS loads.
Also introduce the "object invoke" interface in the SCM driver, to
provide interface to the Qualcomm TEE driver.
* tag 'qcom-drivers-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
firmware: qcom: scm: add support for object invocation
firmware: qcom: tzmem: export shm_bridge create/delete
Link: https://lore.kernel.org/r/20250921020225.595403-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge series from Biju Das <biju.das.jz@bp.renesas.com>:
On RZ/G3E using PSCI, s2ram powers down the SoC. After resume,
reinitialize the hardware for SPI operations.
Also Replace the macro SIMPLE_DEV_PM_OPS->DEFINE_SIMPLE_DEV_PM_OPS macro
and use pm_sleep_ptr(). This lets us drop the check for CONFIG_PM_SLEEP
and __maybe_unused attribute from PM functions.
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Merge series from Haixu Cui <quic_haixcui@quicinc.com>:
This is the 10th version of the virtio SPI Linux driver patch series which is
intended to be compliant with the upcoming virtio specification
version 1.4. The specification can be found in repository:
https://github.com/oasis-tcs/virtio-spec.git branch virtio-1.4.
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Merge series from Jonas Gorski <jonas.gorski@gmail.com>:
This series aims at cleaning up the current multi CS parts and removing
the CS limit per controller that was introduced with the multi CS
support.
To do this, store the assigned chip selects per device in
spi_device::num_chipselects, which allows us to use that instead of
SPI_CS_CNT_MAX for most loops, as well as remove the check for
SPI_INVALID_CS for any chip select.
This should hopefully make it obvious that SPI_CS_CNT_MAX only limits
accesses to arrays indexed by the number of chip selects of a device,
not the controller, and we can remove the check for
spi_controller::num_chipselects being less than SPI_CS_CNT_MAX in device
registration (which was the wrong place to do that anyway).
After having done that, we can reduce SPI_CS_CNT_MAX again to 4 without
breaking devices on higher CS lines.
Finally, rename SPI_CS_CNT_MAX to SPI_DEVICE_CNT_MAX to make it more
clear that this limit only applies to devices, not controllers.
There are still more issues left, but these can be addressed in future
submissions:
* The code allows multi-cs devices for any controller, as long as the
device does not set parallel-memories.
* No current spi controller driver handles logical chip selects other
than the first one, and always use it, regardless what cs_index_mask
says.
* While most spi controllers should be able to handle devices that have
multiple cs that just get enabled selectively, but not at the same
time, there is no way to tell that to the core (ties into the above).
* There is no parallel memories/multi cs flag for devices, so any
implementing driver needs to check the device tree node, making it
impossible to register these kind of devices via platform code.
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Wentong's e-mail address no longer works, remove it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Link: https://patch.msgid.link/20250922120632.10460-4-sakari.ailus@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Rename SPI_CS_CNT_MAX to SPI_DEVICE_CS_CNT_MAX to make it more obvious
that this is the max number of CS per device supported, not per
controller.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-8-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Do not validate spi_controller::num_chipselect against SPI_CS_CNT_MAX
when parsing an spi device firmware node.
Firstly this is the wrong place, and this should be done while
registering/validating the controller. Secondly, there is no reason for
that check, as SPI_CS_CNT_MAX controls the amount of chipselects a
device may have, not a controller may have.
So drop that check as it needlessly limits controllers to SPI_CS_CNT_MAX
number of chipselects.
Likewise, drop the check for number of device chipselects larger than
controller's number of chipselects, as __spi_add_device() will already
catch that as either one of the chip selects will be out of range, or
there is a duplicate one.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-6-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Now that we know the number of chip selects of a device, we can assume
these are valid, and do not need to check them first.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-5-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Using spi_device::num_chipselect, initialize unused device CS as invalid
at registration time in __spi_add_device(), and drop it from the
different allocation paths.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-4-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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There are several places where we need to iterate over a device's
chipselect. To be able to do it efficiently, store the number of
chipselects in spi_device, like we do for controllers.
Since we now use a device supplied value, add a check to make sure it
isn't more than we can support.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-3-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Don't return a positive value when there are too many chipselects.
Fixes: 4d8ff6b0991d ("spi: Add multi-cs memories support in SPI core")
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250915183725.219473-2-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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This is the virtio SPI Linux kernel driver.
Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
Link: https://patch.msgid.link/20250908092348.1283552-4-quic_haixcui@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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If the cached contents of the CHCONF register doesn't have the FORCE bit
set, the setup() function failed to set the relevant idle state of the
SPI_CLK pin. In such case, the SPI_CLK's idle state is reached later with
set_cs(), but it's too late for the first SPI transfer which fails since
the CS is asserted before the clock reaching its idle state.
Add a first write in setup() that always sets the FORCE bit.
Keep the current write afterwards to ensure the FORCE bit won't stay in
the cached contents of the CHCONF register unless it's intended.
Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20250912-omap-spi-fix-v1-1-f925b0d27ede@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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On RZ/G3E using PSCI, s2ram powers down the SoC. After resume,
reinitialize the hardware for SPI operations.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250921112649.104516-3-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Replace SIMPLE_DEV_PM_OPS->DEFINE_SIMPLE_DEV_PM_OPS macro and use
pm_sleep_ptr(). This lets us drop the check for CONFIG_PM_SLEEP, and
reduces kernel size in case CONFIG_PM or CONFIG_PM_SLEEP is disabled,
while increasing build coverage.
Also drop the __maybe_unused attribute from PM functions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250921112649.104516-2-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Dharma Balasubiramani <dharma.b@microchip.com>:
This patch series adds support for SAM9X7 and sama7d65 QSPI controller
along with the SoC-specific capabilities.
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Merge series from Haibo Chen <haibo.chen@nxp.com>:
this patch set add DTR mode support for flexspi.
For DTR mode, flexspi only support 8D-8D-8D mode.
Patch 1~2 extract nxp_fspi_dll_override(), prepare for adding the DTR mode.
in nor suspend, it will disable DTR mode, and enable DTR mode back
in nor resume. this require the flexspi driver has the ability to
set back to dll override mode in STR mode when clock rate < 100MHz.
Patch 3 Add the DDR LUT command support. flexspi use LUT command to handle
the dtr/str mode.
Patch 4 add the logic of sample clock source selection for STR/DTR mode
STR use the default mode 0, sample based on the internal dummy pad.
DTR use the mode 3, sample based on the external DQS pad, so this
board and device connect the DQS pad.
adjust the clock rate for DTR mode, when detect the DDR LUT command,
flexspi will automatically div 2 of the root clock and output to device.
Patch 5 finally add the DTR support in default after the upper 4 patches's
prepareation. Since lx2160a do not implement DQS pad, so can't support
this DTR mode.
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The devm_clk_get_enabled() function prepares and enables the
particular clock, which then automatically gets disabled and
unprepared on probe failure and on device removal.
Use that function instead of devm_clk_get() and remove the
clk_prepare_enable()/clk_disable_unprepare() calls in order
to simplify the code.
This also ensures that the clocks are handled in the correct
order during device removal.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250916-qpic-snand-devm_clk_get_enabled-v1-1-09953493b7f1@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add OCT-DTR mode support in default, since flexspi do not supports
swapping bytes on a 16 bit boundary in OCT-DTR mode, so mark swap16
as false.
lx2160a do not support DQS, so add a quirk to disable DTR mode for this
platform.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-5-bb9fe2a01889@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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flexspi define four mode for sample clock source selection.
Here is the list of modes:
mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
internally
mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
from DQS pad
mode 2: Reserved
mode 3: Flash provided Read strobe and input from DQS pad
In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
otherwise read always get incorrect data.
For DTR mode, flexspi will automatically div 2 of the root clock
and output to device. the formula is:
device_clock = root_clock / (is_dtr ? 2 : 1)
So correct the clock rate setting for DTR mode to get the max
performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-4-bb9fe2a01889@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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For DTR mode, flexspi need to use DDR LUT command, flexspi will switch
to DDR mode when detect the DDR LUT command.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20250917-flexspi-ddr-v2-3-bb9fe2a01889@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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