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Enable 16/32 bits per word support for spi-imx target PIO mode.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251118065012.1418279-1-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>:
This series adds AST2700 support to the ASPEED FMC/SPI driver and
bindings, introduces 64-bit address compatibility, and improves
Quad SPI page programming behavior. It also implements AST2700-specific
segment logic, where range adjustment is not required because the
AST2700 SPI hardware controller already fixes decoding issues on
the existing platforms and adopts an updated scheme.
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On BCM6358 (and also observed on BCM6368) the controller appears to
only generate as many SPI clocks as bytes that have been written into
the TX FIFO. For RX-only transfers the driver programs the transfer
length in SPI_MSG_CTL but does not write anything into the FIFO, so
chip select is deasserted early and the RX transfer segment is never
fully clocked in.
A concrete failing case is a three-transfer MAC address read from
SPI-NOR:
- TX 0x03 (read command)
- TX 3-byte address
- RX 6 bytes (MAC)
In contrast, a two-transfer JEDEC-ID read (0x9f + 6-byte RX) works
because the driver uses prepend_len and writes dummy bytes into the
TX FIFO for the RX part.
Fix this by writing 0xff dummy bytes into the TX FIFO for RX-only
segments so that the number of bytes written to the FIFO matches the
total message length seen by the controller.
Fixes: b17de076062a ("spi/bcm63xx: work around inability to keep CS up")
Signed-off-by: Hang Zhou <929513338@qq.com>
Link: https://patch.msgid.link/tencent_7AC88FCB3076489A4A7E6C2163DF1ACF8D06@qq.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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There are no longer any board files including the DaVinci SPI platform
data header. Let's move the bits and pieces that are used in the driver
into the driver .c file itself and remove the header.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://patch.msgid.link/20251117-davinci-spi-v2-1-cd799d17f04a@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Extend the driver to support the AST2700 SPI controller. Compared to
AST2600, AST2700 has the following characteristics:
- A 64-bit memory address space.
- A 64KB address decoding unit.
- Segment registers now use (start <= range < end) semantics,
which differs slightly from (start <= range <= end) in AST2600.
- Known issues related to address decoding range registers have been
resolved, and the decoding range is now 1GB, which is sufficient.
Therefore, the adjust_window callback is no longer required on AST2700
for range adjustment and bug fixes.
- The SPI clock divider method and timing calibration logic remain
unchanged from AST2600.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251114101042.1520997-5-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Update bus address types from u32 to phys_addr_t to support systems with
64-bit memory address space. This change ensures compatibility with
upcoming SoCs that extend the system bus beyond 32-bit, while maintaining
support for existing platforms.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251114101042.1520997-4-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Ensure the controller switches to quad I/O mode when
spi-tx-bus-width dts property is 4 and the Quad SPI program
opcode (32h or 34h) is used. Without this change, high-bit
data will be lost during page programming.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Link: https://patch.msgid.link/20251114101042.1520997-3-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Both bs->regs and bs->{rx,tx}_io are tagged __iomem, so we shouldn't
cast them to anything else.
Silences the following sparse warning:
drivers/spi/spi-bcm63xx.c:571:22: warning: cast removes address space '__iomem' of expression
drivers/spi/spi-bcm63xx.c:571:19: warning: incorrect type in assignment (different address spaces)
drivers/spi/spi-bcm63xx.c:571:19: expected unsigned char [noderef] [usertype] __iomem *tx_io
drivers/spi/spi-bcm63xx.c:571:19: got unsigned char [usertype] *
drivers/spi/spi-bcm63xx.c:572:22: warning: cast removes address space '__iomem' of expression
drivers/spi/spi-bcm63xx.c:572:19: warning: incorrect type in assignment (different address spaces)
drivers/spi/spi-bcm63xx.c:572:19: expected unsigned char const [noderef] [usertype] __iomem *rx_io
drivers/spi/spi-bcm63xx.c:572:19: got unsigned char const [usertype] *
Fixes: b42dfed83d95 ("spi: add Broadcom BCM63xx SPI controller driver")
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20251116093334.17423-1-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>:
This patch series adds support for the Microchip FPGA CoreSPI "soft" IP
and documents its device tree bindings.
As preparation, the existing Microchip SPI driver is renamed to clearly
indicate that it supports only the Microchip PolarFire SoC "hard" controller.
Although it was originally named with the expectation that it might also
cover the FPGA CoreSPI "soft" IP, the register layouts differ significantly,
so separate drivers are required.
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Merge series from Jun Guo <jun.guo@cixtech.com>:
The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.
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Introduce driver support for the Microchip FPGA CoreSPI IP.
This driver supports only Motorola SPI mode and frame size of 8-bits.
TI/NSC modes and wider frame sizes are not currently supported.
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-4-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The spi-microchip-core.c driver provides support for the Microchip
PolarFire SoC (MPFS) "hard" SPI controller. It was originally named
"core" with the expectation that it might also cover Microchip's
CoreSPI "soft" IP, but that never materialized.
The CoreSPI IP cannot be supported by this driver because its register
layout differs substantially from the MPFS SPI controller. In practice
most of the code would need to be replaced to handle those differences
so keeping the drivers separate is the simpler approach.
The file and internal symbols are renamed to reflect MPFS support and
to free up "spi-microchip-core.c" for CoreSPI driver.
Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-2-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The default FIFO data width of the Cadence SPI IP is 8 bits, but
the hardware supports configurations of 16 bits and 32 bits.
This patch enhances the driver to support communication with both
16-bits and 32-bits FIFO data widths.
Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://patch.msgid.link/20251031073003.3289573-3-jun.guo@cixtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Fix runtime PM usage count underflow caused by calling
pm_runtime_put_autosuspend() twice with only one corresponding
pm_runtime_get_noresume() call. This triggers the warning:
"Runtime PM usage count underflow!"
Remove the duplicate put call to balance the runtime PM reference
counting.
Fixes: 30dbc1c8d50f ("spi: cadence-qspi: defer runtime support on socfpga if reset bit is enabled")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://patch.msgid.link/20251105161146.2019090-3-a-dutta@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The "probe_setup_failed" label calls pm_runtime_disable(), but
pm_runtime_enable() was placed after a possible jump to this label.
When cqspi_setup_flash() fails, control jumps to the label without
pm_runtime_enable() being called, leading to unbalanced PM runtime
reference counting.
Move pm_runtime_enable() and associated calls above the first
possible branch to "probe_setup_failed" to ensure balanced
enable/disable calls across all error paths.
Fixes: 30dbc1c8d50f ("spi: cadence-qspi: defer runtime support on socfpga if reset bit is enabled")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Link: https://patch.msgid.link/20251105161146.2019090-2-a-dutta@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add a TODO comment that ideally the ACPI/gpiolib core code should take care
of setting GPIO direction and/or bias according to ACPI GPIO resources.
If this TODO gets implemented then the acpi_dev_gpio_irq_get() call in
acpi_register_spi_device() can be dropped.
Suggested-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://patch.msgid.link/20251109155340.26199-1-johannes.goede@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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SPI devices using a (relative) slow frequency need a larger time.
For instance, microblaze running at 83.25MHz and performing a
3 bytes transaction using a 10MHz/16 = 625kHz needed this stall
value increased to at least 20. The SPI device is quite slow, but
also is the microblaze, so set this value to 32 to give it even
more margin.
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
Link: https://patch.msgid.link/20251106134545.31942-1-alvaro.gamez@hazent.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Alex Elder <elder@riscstar.com>:
This series adds support for the SpacemiT K1 SoC QSPI. This IP is
generally compatible with the Freescale QSPI driver, requiring three
minor changes to enable it to be supported. The changes are:
- Adding support for optional resets
- Having the clock *not* be disabled when changing its rate
- Allowing the size of storage blocks written to flash chips
to be set to something different from the AHB buffer size
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ECSPI in i.MX51 and i.MX53 support target mode. Current code only support
i.MX53. Remove is_imx53_ecspi() check for target mode to support i.MX51.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Link: https://patch.msgid.link/20251027110256.543314-1-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT
enabled.
Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by
defining the device type data for its QSPI implementation.
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-8-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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In fsl_qspi_default_setup(), four registers define the size of blocks of
data to written to each of four chips that comprise SPI NOR flash storage.
They are currently defined to be the same as the AHB buffer size.
The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
four sizes to be multiples of 1024 bytes.
Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
non-zero, will be used instead of the AHB buffer size to define the size of
these chip regions.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-7-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the
clock when changing its rate. Add a new quirk to indicate that disabling
and enabling the clock should be skipped when changing its rate.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-6-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Change all the needs_*() functions so they are no longer inline, and return
bool rather than int.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-5-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add support for one or more optional exclusive resets. These simply need
to be deasserted at probe time, and can remain that way for the life of the
device.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20251027133008.360237-4-elder@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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In target mode, the clock signal is controlled by the master. Target does
not need to check, calculate and configure the clock frequency division.
The target can directly use the root clock to sample the SCL signal.
Therefore, remove check, calculation and frequency division function of
the clock for target mode.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251024055211.408440-1-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Since sdma hardware configure postpone to transfer phase, have to disable
dma request before dma transfer setup because there is a hardware
limitation on sdma event enable(ENBLn) as below:
"It is thus essential for the Arm platform to program them before any DMA
request is triggered to the SDMA, otherwise an unpredictable combination
of channels may be started."
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Link: https://patch.msgid.link/20251024055320.408482-1-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Since commit d24cfee7f63d ("spi: Fix acpi deferred irq probe"), the
acpi_dev_gpio_irq_get() call gets delayed till spi_probe() is called
on the SPI device.
If there is no driver for the SPI device then the move to spi_probe()
results in acpi_dev_gpio_irq_get() never getting called. This may
cause problems by leaving the GPIO pin floating because this call is
responsible for setting up the GPIO pin direction and/or bias according
to the values from the ACPI tables.
Re-add the removed acpi_dev_gpio_irq_get() in acpi_register_spi_device()
to ensure the GPIO pin is always correctly setup, while keeping the
acpi_dev_gpio_irq_get() call added to spi_probe() to deal with
-EPROBE_DEFER returns caused by the GPIO controller not having a driver
yet.
Link: https://bbs.archlinux.org/viewtopic.php?id=302348
Fixes: d24cfee7f63d ("spi: Fix acpi deferred irq probe")
Cc: stable@vger.kernel.org
Signed-off-by: Hans de Goede <hansg@kernel.org>
Link: https://patch.msgid.link/20251102190921.30068-1-hansg@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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The AHB IO memory for each chip select is mapped using
devm_ioremap(), so it should be unmapped using devm_iounmap()
to ensure proper device-managed resource cleanup.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202510292356.JnTUBxCl-lkp@intel.com/
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://patch.msgid.link/20251105084952.1063489-1-chin-ting_kuo@aspeedtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Vishwaroop A <va@nvidia.com>:
This patch series addresses timeout handling issues in the Tegra QSPI driver
that occur under high system load conditions. We've observed that when CPUs
are saturated (due to error injection, RAS firmware activity, or general CPU
contention), QSPI interrupt handlers can be delayed, causing spurious transfer
failures even though the hardware completed the operation successfully.
These changes have been tested in production environments under various high
load scenarios including RAS testing and CPU saturation workloads.
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Under high system load, QSPI interrupts can be delayed or blocked on the
target CPU, causing wait_for_completion_timeout() to report failure even
though the hardware successfully completed the transfer.
When a timeout occurs, check the QSPI_RDY bit in QSPI_TRANS_STATUS to
determine if the hardware actually completed the transfer. If so, manually
invoke the completion handler to process the transfer successfully instead
of failing it.
This distinguishes lost/delayed interrupts from real hardware timeouts,
preventing unnecessary failures of transfers that completed successfully.
Signed-off-by: Vishwaroop A <va@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://patch.msgid.link/20251028155703.4151791-4-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Extract common cleanup code into dedicated helper functions to simplify
the code and improve readability. This refactoring includes:
- tegra_qspi_reset(): Device reset and interrupt cleanup
- tegra_qspi_dma_stop(): DMA termination and disable
- tegra_qspi_pio_stop(): PIO mode disable
No functional changes. This is purely a code reorganization to prepare
for improved timeout handling in subsequent patches.
Signed-off-by: Vishwaroop A <va@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://patch.msgid.link/20251028155703.4151791-3-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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When the CPU that the QSPI interrupt handler runs on (typically CPU 0)
is excessively busy, it can lead to rare cases of the IRQ thread not
running before the transfer timeout is reached.
While handling the timeouts, any pending transfers are cleaned up and
the message that they correspond to is marked as failed, which leaves
the curr_xfer field pointing at stale memory.
To avoid this, clear curr_xfer to NULL upon timeout and check for this
condition when the IRQ thread is finally run.
While at it, also make sure to clear interrupts on failure so that new
interrupts can be run.
A better, more involved, fix would move the interrupt clearing into a
hard IRQ handler. Ideally we would also want to signal that the IRQ
thread no longer needs to be run after the timeout is hit to avoid the
extra check for a valid transfer.
Fixes: 921fc1838fb0 ("spi: tegra210-quad: Add support for Tegra210 QSPI controller")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vishwaroop A <va@nvidia.com>
Link: https://patch.msgid.link/20251028155703.4151791-2-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Append a newline to the sysfs_emit() output in tle62x0_gpio_show. This
aligns with common kernel conventions and improves readability for
userspace tools that expect newline-terminated values.
Signed-off-by: Zhongqiu Han <zhongqiu.han@oss.qualcomm.com>
Link: https://patch.msgid.link/20251030124755.1828434-1-zhongqiu.han@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Oak Stream PCI ID to the driver list of supported devices.
This patch was originally written by Zeng Guang.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://patch.msgid.link/20251029065020.2920213-1-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The spi subsystem has tracing, which is very convenient when debugging
problems. Add tracing for spi-mem too so that accesses that skip the spi
subsystem can still be seen.
The format is roughly based on the existing spi tracing. We don't bother
tracing the op's address because the tracing happens while the memory is
locked, so there can be no confusion about the matching of start and
stop. The conversion of cmd/addr/dummy to an array is directly analogous
to the conversion in the latter half of spi_mem_exec_op.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://patch.msgid.link/20251021144702.1582397-1-sean.anderson@linux.dev
Signed-off-by: Mark Brown <broonie@kernel.org>
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Marking the qcom_spi_ecc_engine_ops_pipelined as const provides
memory protection by preventing accidental modification of critical
function pointers at runtime. It also enables memory optimization
by placing the structure in read-only sections and improves code safety
by explicitly documenting the design intent that these operations
should not change after initialization.
Signed-off-by: Can Peng <pengcan@kylinos.cn>
Link: https://patch.msgid.link/20251023024250.3181084-1-pengcan@kylinos.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Intel Wildcat Lake SPI serial flash PCI ID to the list of supported
devices.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://patch.msgid.link/20251020145415.3377022-4-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Intel Arrow Lake-H PCI ID to the driver list of supported devices.
This is the same controller found in previous generations.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://patch.msgid.link/20251020145415.3377022-3-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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With the recent hardware the flash component density can be increased to
128M. Update the driver to support this. While there log a warning if we
encounter an unsupported value in this field.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://patch.msgid.link/20251020145415.3377022-2-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge series from Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>:
This patch series greatly improve airoha snfi driver and fix a
number of serious bugs.
Fixed bugs:
* Fix reading/writing of flashes with more than one plane per lun
* Fill the buffer with 0xff before writing
* Fix reading of flashes supporting continuous reading mode
* Fix error paths
Improvements:
* Add support of dual/quad wires spi modes in exec_op(). This also
fix flash reading/writing if dirmap can't be created.
* Support of dualio/quadio flash reading commands
* Remove dirty hack that reads flash page settings from SNFI registers
during driver startup
* Add support of EN7523 SoC
Patched kernel tests:
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_oobtest.ko dev=1
[ 263.191711]
[ 263.193218] =================================================
[ 263.199014] mtd_oobtest: MTD device: 1
[ 263.202768] mtd_oobtest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 263.216791] mtd_test: scanning for bad eraseblocks
[ 263.221956] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 263.227361] mtd_oobtest: test 1 of 5
[ 265.077216] mtd_oobtest: writing OOBs of whole device
[ 265.121767] mtd_oobtest: written up to eraseblock 0
[ 275.174147] mtd_oobtest: written up to eraseblock 256
[ 285.210279] mtd_oobtest: written up to eraseblock 512
[ 295.241724] mtd_oobtest: written up to eraseblock 768
[ 305.280167] mtd_oobtest: written up to eraseblock 1024
[ 315.326883] mtd_oobtest: written up to eraseblock 1280
[ 325.364049] mtd_oobtest: written up to eraseblock 1536
[ 335.398609] mtd_oobtest: written up to eraseblock 1792
[ 345.358981] mtd_oobtest: written 2047 eraseblocks
[ 345.363694] mtd_oobtest: verifying all eraseblocks
[ 345.386088] mtd_oobtest: verified up to eraseblock 0
[ 349.830833] mtd_oobtest: verified up to eraseblock 256
[ 354.276245] mtd_oobtest: verified up to eraseblock 512
[ 358.721496] mtd_oobtest: verified up to eraseblock 768
[ 363.166881] mtd_oobtest: verified up to eraseblock 1024
[ 367.612694] mtd_oobtest: verified up to eraseblock 1280
[ 372.058211] mtd_oobtest: verified up to eraseblock 1536
[ 376.503820] mtd_oobtest: verified up to eraseblock 1792
[ 380.914843] mtd_oobtest: verified 2047 eraseblocks
[ 380.919660] mtd_oobtest: test 2 of 5
[ 384.202620] mtd_oobtest: writing OOBs of whole device
[ 384.247584] mtd_oobtest: written up to eraseblock 0
[ 394.305121] mtd_oobtest: written up to eraseblock 256
[ 404.342199] mtd_oobtest: written up to eraseblock 512
[ 414.374204] mtd_oobtest: written up to eraseblock 768
[ 424.409891] mtd_oobtest: written up to eraseblock 1024
[ 434.453378] mtd_oobtest: written up to eraseblock 1280
[ 444.494321] mtd_oobtest: written up to eraseblock 1536
[ 454.534480] mtd_oobtest: written up to eraseblock 1792
[ 464.490962] mtd_oobtest: written 2047 eraseblocks
[ 464.495681] mtd_oobtest: verifying all eraseblocks
[ 464.518015] mtd_oobtest: verified up to eraseblock 0
[ 468.955635] mtd_oobtest: verified up to eraseblock 256
[ 473.395502] mtd_oobtest: verified up to eraseblock 512
[ 477.834373] mtd_oobtest: verified up to eraseblock 768
[ 482.272717] mtd_oobtest: verified up to eraseblock 1024
[ 486.712148] mtd_oobtest: verified up to eraseblock 1280
[ 491.150704] mtd_oobtest: verified up to eraseblock 1536
[ 495.589439] mtd_oobtest: verified up to eraseblock 1792
[ 499.993138] mtd_oobtest: verified 2047 eraseblocks
[ 499.997951] mtd_oobtest: test 3 of 5
[ 503.404228] mtd_oobtest: writing OOBs of whole device
[ 503.448822] mtd_oobtest: written up to eraseblock 0
[ 513.480773] mtd_oobtest: written up to eraseblock 256
[ 523.489361] mtd_oobtest: written up to eraseblock 512
[ 533.506896] mtd_oobtest: written up to eraseblock 768
[ 543.506268] mtd_oobtest: written up to eraseblock 1024
[ 553.506503] mtd_oobtest: written up to eraseblock 1280
[ 563.511266] mtd_oobtest: written up to eraseblock 1536
[ 573.519567] mtd_oobtest: written up to eraseblock 1792
[ 583.455111] mtd_oobtest: written 2047 eraseblocks
[ 583.459837] mtd_oobtest: verifying all eraseblocks
[ 583.499358] mtd_oobtest: verified up to eraseblock 0
[ 592.382953] mtd_oobtest: verified up to eraseblock 256
[ 601.267297] mtd_oobtest: verified up to eraseblock 512
[ 610.150907] mtd_oobtest: verified up to eraseblock 768
[ 619.034702] mtd_oobtest: verified up to eraseblock 1024
[ 627.919683] mtd_oobtest: verified up to eraseblock 1280
[ 636.821168] mtd_oobtest: verified up to eraseblock 1536
[ 645.705487] mtd_oobtest: verified up to eraseblock 1792
[ 654.520336] mtd_oobtest: verified 2047 eraseblocks
[ 654.525134] mtd_oobtest: test 4 of 5
[ 657.578146] mtd_oobtest: attempting to start write past end of OOB
[ 657.584336] mtd_oobtest: an error is expected...
[ 657.588974] mtd_oobtest: error occurred as expected
[ 657.593848] mtd_oobtest: attempting to start read past end of OOB
[ 657.599953] mtd_oobtest: an error is expected...
[ 657.604569] mtd_oobtest: error occurred as expected
[ 657.609450] mtd_oobtest: attempting to write past end of device
[ 657.615367] mtd_oobtest: an error is expected...
[ 657.619990] mtd_oobtest: error occurred as expected
[ 657.624864] mtd_oobtest: attempting to read past end of device
[ 657.630715] mtd_oobtest: an error is expected...
[ 657.635333] mtd_oobtest: error occurred as expected
[ 657.641043] mtd_oobtest: attempting to write past end of device
[ 657.646966] mtd_oobtest: an error is expected...
[ 657.651574] mtd_oobtest: error occurred as expected
[ 657.656451] mtd_oobtest: attempting to read past end of device
[ 657.662277] mtd_oobtest: an error is expected...
[ 657.666901] mtd_oobtest: error occurred as expected
[ 657.671774] mtd_oobtest: test 5 of 5
[ 659.382333] mtd_oobtest: writing OOBs of whole device
[ 659.388056] mtd_oobtest: written up to eraseblock 0
[ 659.393526] mtd_oobtest: written up to eraseblock 0
[ 659.704525] mtd_oobtest: written up to eraseblock 256
[ 659.710187] mtd_oobtest: written up to eraseblock 256
[ 660.021093] mtd_oobtest: written up to eraseblock 512
[ 660.026752] mtd_oobtest: written up to eraseblock 512
[ 660.338427] mtd_oobtest: written up to eraseblock 768
[ 660.344048] mtd_oobtest: written up to eraseblock 768
[ 660.655718] mtd_oobtest: written up to eraseblock 1024
[ 660.661462] mtd_oobtest: written up to eraseblock 1024
[ 660.970676] mtd_oobtest: written up to eraseblock 1280
[ 660.976386] mtd_oobtest: written up to eraseblock 1280
[ 661.286858] mtd_oobtest: written up to eraseblock 1536
[ 661.292587] mtd_oobtest: written up to eraseblock 1536
[ 661.605397] mtd_oobtest: written up to eraseblock 1792
[ 661.611142] mtd_oobtest: written up to eraseblock 1792
[ 661.918754] mtd_oobtest: written 2046 eraseblocks
[ 661.923458] mtd_oobtest: verifying all eraseblocks
[ 661.928812] mtd_oobtest: verified up to eraseblock 0
[ 662.072499] mtd_oobtest: verified up to eraseblock 256
[ 662.216152] mtd_oobtest: verified up to eraseblock 512
[ 662.359956] mtd_oobtest: verified up to eraseblock 768
[ 662.503238] mtd_oobtest: verified up to eraseblock 1024
[ 662.646847] mtd_oobtest: verified up to eraseblock 1280
[ 662.790603] mtd_oobtest: verified up to eraseblock 1536
[ 662.934269] mtd_oobtest: verified up to eraseblock 1792
[ 663.076329] mtd_oobtest: verified 2046 eraseblocks
[ 663.081114] mtd_oobtest: finished with 0 errors
[ 663.085647] =================================================
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_pagetest.ko dev=1
[ 1142.213082]
[ 1142.214590] =================================================
[ 1142.220433] mtd_pagetest: MTD device: 1
[ 1142.224278] mtd_pagetest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 1142.238388] mtd_test: scanning for bad eraseblocks
[ 1142.243536] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 1142.248935] mtd_pagetest: erasing whole device
[ 1143.962562] mtd_pagetest: erased 2047 eraseblocks
[ 1143.967301] mtd_pagetest: writing whole device
[ 1144.011729] mtd_pagetest: written up to eraseblock 0
[ 1154.137933] mtd_pagetest: written up to eraseblock 256
[ 1164.265201] mtd_pagetest: written up to eraseblock 512
[ 1174.393365] mtd_pagetest: written up to eraseblock 768
[ 1184.525700] mtd_pagetest: written up to eraseblock 1024
[ 1194.650920] mtd_pagetest: written up to eraseblock 1280
[ 1204.773676] mtd_pagetest: written up to eraseblock 1536
[ 1214.896934] mtd_pagetest: written up to eraseblock 1792
[ 1224.942600] mtd_pagetest: written 2047 eraseblocks
[ 1224.947410] mtd_pagetest: verifying all eraseblocks
[ 1225.053133] mtd_pagetest: verified up to eraseblock 0
[ 1250.760034] mtd_pagetest: verified up to eraseblock 256
[ 1276.448242] mtd_pagetest: verified up to eraseblock 512
[ 1302.138825] mtd_pagetest: verified up to eraseblock 768
[ 1327.824020] mtd_pagetest: verified up to eraseblock 1024
[ 1353.532178] mtd_pagetest: verified up to eraseblock 1280
[ 1379.234385] mtd_pagetest: verified up to eraseblock 1536
[ 1404.943865] mtd_pagetest: verified up to eraseblock 1792
[ 1430.468816] mtd_pagetest: verified 2047 eraseblocks
[ 1430.473702] mtd_pagetest: crosstest
[ 1430.477717] mtd_pagetest: reading page at 0x0
[ 1430.482328] mtd_pagetest: reading page at 0xffdf800
[ 1430.487469] mtd_pagetest: reading page at 0x0
[ 1430.492084] mtd_pagetest: verifying pages read at 0x0 match
[ 1430.497668] mtd_pagetest: crosstest ok
[ 1430.501409] mtd_pagetest: erasecrosstest
[ 1430.505323] mtd_pagetest: erasing block 0
[ 1430.511511] mtd_pagetest: writing 1st page of block 0
[ 1430.517166] mtd_pagetest: reading 1st page of block 0
[ 1430.522505] mtd_pagetest: verifying 1st page of block 0
[ 1430.527739] mtd_pagetest: erasing block 0
[ 1430.532565] mtd_pagetest: writing 1st page of block 0
[ 1430.538229] mtd_pagetest: erasing block 2046
[ 1430.544181] mtd_pagetest: reading 1st page of block 0
[ 1430.549498] mtd_pagetest: verifying 1st page of block 0
[ 1430.554718] mtd_pagetest: erasecrosstest ok
[ 1430.558900] mtd_pagetest: erasetest
[ 1430.562381] mtd_pagetest: erasing block 0
[ 1430.567208] mtd_pagetest: writing 1st page of block 0
[ 1430.572858] mtd_pagetest: erasing block 0
[ 1430.577680] mtd_pagetest: reading 1st page of block 0
[ 1430.582990] mtd_pagetest: verifying 1st page of block 0 is all 0xff
[ 1430.589279] mtd_pagetest: erasetest ok
[ 1430.593023] mtd_pagetest: finished with 0 errors
[ 1430.597651] =================================================
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_readtest.ko dev=1
[ 1478.691648]
[ 1478.693158] =================================================
[ 1478.698981] mtd_readtest: MTD device: 1
[ 1478.702829] mtd_readtest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 1478.716939] mtd_test: scanning for bad eraseblocks
[ 1478.722072] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 1478.727475] mtd_readtest: testing page read
[ 1548.352125] mtd_readtest: finished
[ 1548.355553] =================================================
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_speedtest.ko dev=1
[ 1617.353002]
[ 1617.354511] =================================================
[ 1617.360332] mtd_speedtest: MTD device: 1
[ 1617.364258] mtd_speedtest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 1617.380150] mtd_test: scanning for bad eraseblocks
[ 1617.385428] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 1621.021861] mtd_speedtest: testing eraseblock write speed
[ 1700.915306] mtd_speedtest: eraseblock write speed is 3279 KiB/s
[ 1700.921250] mtd_speedtest: testing eraseblock read speed
[ 1734.931886] mtd_speedtest: eraseblock read speed is 7705 KiB/s
[ 1738.682742] mtd_speedtest: testing page write speed
[ 1818.818644] mtd_speedtest: page write speed is 3269 KiB/s
[ 1818.824058] mtd_speedtest: testing page read speed
[ 1852.913595] mtd_speedtest: page read speed is 7687 KiB/s
[ 1856.674492] mtd_speedtest: testing 2 page write speed
[ 1936.437284] mtd_speedtest: 2 page write speed is 3285 KiB/s
[ 1936.442869] mtd_speedtest: testing 2 page read speed
[ 1970.498124] mtd_speedtest: 2 page read speed is 7694 KiB/s
[ 1970.503624] mtd_speedtest: Testing erase speed
[ 1974.343389] mtd_speedtest: erase speed is 68316 KiB/s
[ 1974.348479] mtd_speedtest: Testing 2x multi-block erase speed
[ 1976.068855] mtd_speedtest: 2x multi-block erase speed is 152811 KiB/s
[ 1976.075309] mtd_speedtest: Testing 4x multi-block erase speed
[ 1977.790232] mtd_speedtest: 4x multi-block erase speed is 153301 KiB/s
[ 1977.796693] mtd_speedtest: Testing 8x multi-block erase speed
[ 1979.511905] mtd_speedtest: 8x multi-block erase speed is 153273 KiB/s
[ 1979.518367] mtd_speedtest: Testing 16x multi-block erase speed
[ 1981.230700] mtd_speedtest: 16x multi-block erase speed is 153539 KiB/s
[ 1981.237249] mtd_speedtest: Testing 32x multi-block erase speed
[ 1982.948381] mtd_speedtest: 32x multi-block erase speed is 153648 KiB/s
[ 1982.954918] mtd_speedtest: Testing 64x multi-block erase speed
[ 1984.665992] mtd_speedtest: 64x multi-block erase speed is 153655 KiB/s
[ 1984.672531] mtd_speedtest: finished
[ 1984.676054] =================================================
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_stresstest.ko dev=1
[ 2190.651750]
[ 2190.653263] =================================================
[ 2190.659087] mtd_stresstest: MTD device: 1
[ 2190.663105] mtd_stresstest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 2190.679846] mtd_test: scanning for bad eraseblocks
[ 2190.684981] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 2190.690389] mtd_stresstest: doing operations
[ 2190.694655] mtd_stresstest: 0 operations done
[ 2214.262705] mtd_stresstest: 1024 operations done
[ 2239.019612] mtd_stresstest: 2048 operations done
[ 2262.820899] mtd_stresstest: 3072 operations done
[ 2285.061376] mtd_stresstest: 4096 operations done
[ 2308.297322] mtd_stresstest: 5120 operations done
[ 2330.530459] mtd_stresstest: 6144 operations done
[ 2352.651759] mtd_stresstest: 7168 operations done
[ 2375.188275] mtd_stresstest: 8192 operations done
[ 2397.738174] mtd_stresstest: 9216 operations done
[ 2414.792572] mtd_stresstest: finished, 10000 operations done
[ 2414.798257] =================================================
Speed test of original driver (with patch to fix support of flashes
with more than one plane per lun)
root@OpenWrt:/lib/modules/6.6.79# insmod mtd_speedtest.ko dev=1
[ 2894.142208]
[ 2894.143719] =================================================
[ 2894.149556] mtd_speedtest: MTD device: 1
[ 2894.153486] mtd_speedtest: MTD device size 268304384, eraseblock size 131072, page size 2048, count of eraseblocks 2047, pages per eraseblock 64, OOB size 128
[ 2894.168888] mtd_test: scanning for bad eraseblocks
[ 2894.174023] mtd_test: scanned 2047 eraseblocks, 0 are bad
[ 2897.500416] mtd_speedtest: testing eraseblock write speed
[ 2977.807233] mtd_speedtest: eraseblock write speed is 3262 KiB/s
[ 2977.813171] mtd_speedtest: testing eraseblock read speed
[ 3013.906597] mtd_speedtest: eraseblock read speed is 7260 KiB/s
[ 3017.440320] mtd_speedtest: testing page write speed
[ 3097.833394] mtd_speedtest: page write speed is 3259 KiB/s
[ 3097.838812] mtd_speedtest: testing page read speed
[ 3134.004981] mtd_speedtest: page read speed is 7245 KiB/s
[ 3137.538423] mtd_speedtest: testing 2 page write speed
[ 3217.906288] mtd_speedtest: 2 page write speed is 3260 KiB/s
[ 3217.911883] mtd_speedtest: testing 2 page read speed
[ 3254.049757] mtd_speedtest: 2 page read speed is 7251 KiB/s
[ 3254.055254] mtd_speedtest: Testing erase speed
[ 3257.599146] mtd_speedtest: erase speed is 74027 KiB/s
[ 3257.604213] mtd_speedtest: Testing 2x multi-block erase speed
[ 3259.320945] mtd_speedtest: 2x multi-block erase speed is 153139 KiB/s
[ 3259.327413] mtd_speedtest: Testing 4x multi-block erase speed
[ 3261.044585] mtd_speedtest: 4x multi-block erase speed is 153098 KiB/s
[ 3261.051047] mtd_speedtest: Testing 8x multi-block erase speed
[ 3262.786520] mtd_speedtest: 8x multi-block erase speed is 151479 KiB/s
[ 3262.792979] mtd_speedtest: Testing 16x multi-block erase speed
[ 3264.509898] mtd_speedtest: 16x multi-block erase speed is 153130 KiB/s
[ 3264.516454] mtd_speedtest: Testing 32x multi-block erase speed
[ 3266.233403] mtd_speedtest: 32x multi-block erase speed is 153125 KiB/s
[ 3266.239961] mtd_speedtest: Testing 64x multi-block erase speed
[ 3267.957985] mtd_speedtest: 64x multi-block erase speed is 153029 KiB/s
[ 3267.964525] mtd_speedtest: finished
[ 3267.968039] =================================================
It looks like a patched driver is a bit faster
write speed: 3260 KiB/s vs 3277 KiB/s
read speed: 7252 KiB/s vs 7695 KiB/s
|
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The platform_get_resource() function doesn't return error pointers, it
returns NULL on error. Update the error checking to match.
Fixes: 64d87ccfae33 ("spi: aspeed: Only map necessary address window region")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://patch.msgid.link/aPJpEnfK31pHz8_w@stanley.mountain
Signed-off-by: Mark Brown <broonie@kernel.org>
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During writing, the entire flash page (including OOB) will be updated
with the values from the temporary buffer, so we need to fill the
untouched areas of the buffer with 0xff value to prevent accidental
data overwriting.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-14-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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driver startup
The spinand driver do 3 type of dirmap requests:
* read/write whole flash page without oob
(offs = 0, len = page_size)
* read/write whole flash page including oob
(offs = 0, len = page_size + oob_size)
* read/write oob area only
(offs = page_size, len = oob_size)
The trick is:
* read/write a single "sector"
* set a custom sector size equal to offs + len. It's a bit safer to
rounded up "sector size" value 64.
* set the transfer length equal to custom sector size
And it works!
Thus we can remove a dirty hack that reads flash page settings from
SNFI registers during driver startup. Also airoha_snand_adjust_op_size()
function becomes unnecessary.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Link: https://patch.msgid.link/20251012121707.2296160-13-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
|
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Set custom sector size equal to flash page size including oob. Thus we
will always read a single sector. The maximum custom sector size is
8187, so all possible flash sector sizes are supported.
This patch is a necessary step to avoid reading flash page settings
from SNFI registers during driver startup.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-12-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
|
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REG_SPI_NFI_SECCUS_SIZE registers
This just reduce the number of modification of REG_SPI_NFI_CNFG and
REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation.
This patch is a necessary step to avoid reading flash page settings
from SNFI registers during driver startup.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-11-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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spi-airoha-snfi uses custom sector size in REG_SPI_NFI_SECCUS_SIZE
register, so setting of page/oob sizes in REG_SPI_NFI_PAGEFMT is not
required.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Link: https://patch.msgid.link/20251012121707.2296160-10-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
|
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Airoha snfi spi controller supports acceleration of DUAL/QUAD
operations, but does not supports DUAL_IO/QUAD_IO operations.
Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
so we can issue corresponding DUAL/QUAD operation instead of
DUAL_IO/QUAD_IO one.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-9-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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Makes dirmap writing looks similar to dirmap reading. Just a minor
refactoring, no behavior change is expected.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Link: https://patch.msgid.link/20251012121707.2296160-8-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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The code switches to dma at the start of dirmap operation and returns
to non-dma at the end of dirmap operation, so an additional switch to
non-dma at the start of dirmap write is not required.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-5-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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The "length < 160" restriction is not needed because airoha_snand_write_data()
and airoha_snand_read_data() will properly handle data transfers above
SPI_MAX_TRANSFER_SIZE.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251012121707.2296160-3-mikhail.kshevetskiy@iopsys.eu
Signed-off-by: Mark Brown <broonie@kernel.org>
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