summaryrefslogtreecommitdiff
path: root/drivers/soc
AgeCommit message (Collapse)Author
2022-12-05soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done responseAbel Vesa
The RSC interrupt is issued only after the request is complete. For fire-n-forget requests, the irq-done interrupt is sent after issuing the RPMH request and for response-required request, the interrupt is triggered only after all the requests are complete. These unnecessary checks in the interrupt handler issues AHB reads from a critical path. Lets remove them and clean up error handling in rpmh_request data structures. Co-developed-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-2-abel.vesa@linaro.org
2022-12-05soc: qcom: rpmh-rsc: Add support for RSC v3 register offsetsAbel Vesa
The SM8550 RSC has a new set of register offsets due to its version bump. So read the version from HW and use the proper register offsets based on that. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-1-abel.vesa@linaro.org
2022-12-05soc: qcom: rpmhpd: Add SM8550 power domainsAbel Vesa
Add the power domains exposed by RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-3-abel.vesa@linaro.org
2022-12-05soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id tableAngeloGioacchino Del Regno
Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-8-angelogioacchino.delregno@collabora.com
2022-12-05oc: ti: ti_sci_inta_msi: Switch to domain id aware MSI functionsAhmed S. Darwish
Switch to the new domain id aware interfaces to phase out the previous ones. Remove the domain check as it happens in the core code now. No functional change. Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221124230314.634800247@linutronix.de
2022-12-05genirq/msi: Rename msi_add_msi_desc() to msi_insert_msi_desc()Thomas Gleixner
This reflects the functionality better. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221124230314.103554618@linutronix.de
2022-12-05soc: fsl: qe: request pins non-exclusivelyDmitry Torokhov
Commit 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") changed qe_pin_request() to request and hold GPIO corresponding to a given pin. Unfortunately this does not work, as fhci-hcd requests these GPIOs first, befor calling qe_pin_request() (see drivers/usb/host/fhci-hcd.c::of_fhci_probe()). To fix it change qe_pin_request() to request GPIOs non-exclusively, and free them once the code determines GPIO controller and offset for each GPIO/pin. Also reaching deep into gpiolib implementation is not the best idea. We should either export gpio_chip_hwgpio() or keep converting to the global gpio numbers space until we fix the driver to implement proper pin control. Fixes: 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/Y400YXnWBdz1e/L5@google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-12-05soc: qcom: geni-se: add support for I2C Master Hub wrapper variantNeil Armstrong
The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Add the clock list for the I2C Master Hub variant to a new desc struct then pass it through the I2C Master Hub compatible match data. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-12-05soc: qcom: geni-se: add desc struct to specify clocks from device match dataNeil Armstrong
The I2C Master Hub is a stripped down version of the GENI Serial Engine QUP Wrapper Controller but only supporting I2C serial engines without DMA support. Prepare support for the I2C Master Hub variant by moving the required clocks list to a new desc struct then passing it through the compatible match data. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2022-12-04pxa: Remove dev_err() after platform_get_irq()zhang songyi
There is no need to call the dev_err() function directly to print a custom message when handling an error from either the platform_get_irq() or platform_get_irq_byname() functions as both are going to display an appropriate error message in case of a failure. Signed-off-by: zhang songyi <zhang.songyi@zte.com.cn> Reviewed-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/202212021042043546303@zte.com.cn Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-30Merge tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux ↵Arnd Bergmann
into soc/drivers Apple SoC RTKit/SART updates for 6.2. Just two minor correctness nits reported by the kernel test robot. * tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux: soc: apple: rtkit: Stop casting function pointer signatures soc: apple: sart: Stop casting function pointer signatures Link: https://lore.kernel.org/r/57f84134-8645-35f6-2427-ee683800c413@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-28soc: apple: rtkit: Stop casting function pointer signaturesSven Peter
Fixes: 9bd1d9a0d8bb ("soc: apple: Add RTKit IPC library") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2022-11-28soc: apple: sart: Stop casting function pointer signaturesSven Peter
Fixes: b170143ae111 ("soc: apple: Add SART driver") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2022-11-23soc: fsl: dpio: Remove linux/msi.h includeThomas Gleixner
Nothing in this file needs anything from linux/msi.h Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20221113202428.760225831@linutronix.de
2022-11-23Merge tag 'ti-driver-soc-for-v6.2-v2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers TI SoC driver updates for v6.2 v2 * Minor bugfixes for knav_qmss_queue, smartreflex drivers * API optimizations including using devm, bitmap apis to ti-sci, soc-info drivers * k3-ringacc can now be built as modules for certain distros that mandate such usage. * k3-socinfo can now detect AM62A SoCs. * tag 'ti-driver-soc-for-v6.2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: k3-socinfo: Add AM62Ax JTAG ID soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe firmware: ti_sci: Use devm_bitmap_zalloc when applicable soc: ti: k3-ringacc: Allow the driver to be built as module firmware: ti_sci: Fix polled mode during system suspend firmware: ti_sci: Use the non-atomic bitmap API when applicable firmware: ti_sci: Use the bitmap API to allocate bitmaps drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as static Link: https://lore.kernel.org/r/20221122223856.fwackjg7fbd5jcz7@wannabe Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-23Merge tag 'qcom-drivers-for-6.2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for 6.2 The qcom,msm-id and qcom,board-id DeviceTree properties are documented, to allow them to be used in configurations or devices requiring these and the socinfo driver is updated to reuse the introduced identifiers. The rpmh-rsc driver is extended to register for PM runtime notifications from the CPU clusters, in order to submit sleep and wake votes the last core in a cluster is being powered down. A mechanism for keeping rpmhpd resources voted until sync_state is introduced, this ensures that power-domains required during boot are kept enabled. The rpmhpd power-domains for SDM670 are also added. Support for the new QDU1000/QRU1000 platform is introduced in the rpmhpd and socinfo drivers. The APR driver gains missing error handling. QMI message descriptors in the PDR driver are made const. Support for the RPM found in SM6375 is added. The SPM driver gains support for MSM8939 and MSM8976 platforms. The stats and command-db drvers are marked as not having PM support. * tag 'qcom-drivers-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits) dt-bindings: firmware: scm: add sdm670 compatible soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup soc: qcom: rpmh-rsc: Save base address of drv PM: domains: Store the next hrtimer wakeup in genpd soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976 soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000 soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding dt-bindings: qcom: smp2p: Add WPSS node names to pattern property soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2 soc: qcom: llcc: make irq truly optional soc: qcom: spm: Add MSM8939 SPM register data dt-bindings: soc: qcom: spm: Add MSM8939 CPU compatible dt-bindings: soc: qcom: aoss: Add sc8280xp compatible dt-bindings: firmware: document Qualcomm SM6375 SCM ... Link: https://lore.kernel.org/r/20221122202748.1854487-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-22soc: ti: k3-socinfo: Add AM62Ax JTAG IDVignesh Raghavendra
Add JTAG ID entry to help identify AM62Ax SoC in kernel. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221119152447.241166-1-vigneshr@ti.com
2022-11-22Merge tag 'v6.1-next-soc' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers mmsys: - add support for MT8186 - add correct compatible solution for vdosys[0,1] on MT8195 pmic wrapper: - add support for MT8365 * tag 'v6.1-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: Add deprecated compatible to mmsys soc: mediatek: pwrap: add mt8365 SoC support soc: mediatek: pwrap: add support for sys & tmr clocks dt-bindings: soc: mediatek: pwrap: add MT8365 SoC bindings soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0" dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func Link: https://lore.kernel.org/r/cc756001-a942-90b0-b79d-62c1fc189828@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-22Merge tag 'tegra-for-6.2-soc-v2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v6.2-rc1 In addition to a number of improvements and cleanups this contains a fix for the FUSE access on newer chips, adds Tegra234 I/O pad support and fixes various issues with wake events. The SoC sysfs revision attribute is updated to include the platform information so drivers can check for silicon vs. pre-silicon, among other things. * tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Remove redundant dev_err call soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err firmware: tegra: include IVC header file only once soc/tegra: cbb: Check firewall before enabling error reporting soc/tegra: cbb: Add checks for potential out of bound errors soc/tegra: cbb: Update slave maps for Tegra234 soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194 soc/tegra: fuse: Use platform info with SoC revision soc/tegra: pmc: Process wake events during resume soc/tegra: pmc: Fix dual edge triggered wakes soc/tegra: pmc: Add I/O pad table for Tegra234 soc/tegra: fuse: Add nvmem keepout list soc/tegra: fuse: Use SoC specific nvmem cells soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY Link: https://lore.kernel.org/r/20221121171239.2041835-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-22Merge tag 'riscv-soc-for-v6.2-mw0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.2 SiFive: - add probe error handling to the ccache driver * tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init() soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init() soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() Link: https://lore.kernel.org/r/Y3u0Oydiv2Wauda2@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21soc: mediatek: Add deprecated compatible to mmsysMatthias Brugger
For backward compatibility we add the deprecated compatible. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221111082912.14557-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: pwrap: add mt8365 SoC supportFabien Parent
Add PMIC Wrap support for MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221031093401.22916-4-fchiby@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: pwrap: add support for sys & tmr clocksFabien Parent
MT8365 requires an extra 2 clocks to be enabled to behave correctly. Add support these 2 clocks, they are made optional since they seem to be present only on MT8365. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221031093401.22916-3-fchiby@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21soc: mediatek: add mtk-mmsys support for mt8195 vdosys0Jason-JH.Lin
1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0". 2. Add mt8195 routing table settings of vdosys0. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220927152704.12018-4-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0"Jason-JH.Lin
This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254. Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys" to "mediatek,mt8195-vdosys0", we have to revert this patch and send a new patch with the new compatible. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Link: https://lore.kernel.org/r/20220927152704.12018-3-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-11-21Merge tag 'imx-drivers-6.2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers i.MX drivers change for 6.2: - Improve imx8m-blk-ctrl driver to allow deferred probe in case that 'bus' genpd is not yet ready. - Add missing USB_1_PHY PD for i.MX scu-pd firmware driver. - Add GENPD_FLAG_ACTIVE_WAKEUP flag for i.MX8MM/N in GPCv2 driver, so that the power domain remains on if USB remote wakeup is enabled. * tag 'imx-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/n firmware: imx: scu-pd: add missed USB_1_PHY pd soc: imx: imx8m-blk-ctrl: Defer probe if 'bus' genpd is not yet ready Link: https://lore.kernel.org/r/20221119125733.32719-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-21Merge tag 'renesas-drivers-for-v6.2-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.2 (take two) - Add support for identifying the SoC revision on RZ/V2M. * tag 'renesas-drivers-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Identify RZ/V2M SoC Link: https://lore.kernel.org/r/cover.1668788925.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-17soc/tegra: cbb: Remove redundant dev_err callShang XiaoJing
devm_ioremap_resource() prints error message in itself. Remove the dev_err call to avoid redundant error message. Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_errLiu Shixin
Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No functional change. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17soc: renesas: Identify RZ/V2M SoCPhil Edworthy
Add support for identifying the RZ/V2M (R9A09G011) SoC. Note that the SoC does not have a identification register. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> [biju: removed config changes ] Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17genirq: Get rid of GENERIC_MSI_IRQ_DOMAINThomas Gleixner
Adjust to reality and remove another layer of pointless Kconfig indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve all purposes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20221111122014.524842979@linutronix.de
2022-11-14soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probeZhang Qilong
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 984aa6dbf4ca ("OMAP3: PM: Adding smartreflex driver support.") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-3-zhangqilong3@huawei.com
2022-11-14soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probeZhang Qilong
The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 41f93af900a2 ("soc: ti: add Keystone Navigator QMSS driver") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-2-zhangqilong3@huawei.com
2022-11-14Merge tag 'renesas-arm-soc-for-v6.2-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc Renesas ARM SoC updates for v6.2 - Drop selecting GPIOLIB and PINCTRL, which are already automatically selected as part of the SOC_RENESAS config option in drivers/soc/renesas/Kconfig. * tag 'renesas-arm-soc-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: renesas: Drop selecting GPIOLIB and PINCTRL ARM: shmobile: Drop selecting GPIOLIB and PINCTRL soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS Link: https://lore.kernel.org/r/cover.1667558746.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14soc: loongson: add GUTS driver for loongson-2 platformsYinbo Zhu
The global utilities block controls PCIE device enabling, alternate function selection for multiplexed signals, consistency of HDA, USB and PCIE, configuration of memory controller, rtc controller, lio controller, and clock control. This patch adds a driver to manage and access global utilities block for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading firmware configuration by default, should eventually be added into this driver as well. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14Merge tag 'renesas-drivers-for-v6.2-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v6.2 - Let SOC_RENESAS select GPIOLIB and PINCTRL, so this does not have to be handled in two (soon three: arm/arm64/riscv), places. * tag 'renesas-drivers-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS Link: https://lore.kernel.org/r/cover.1667558747.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14soc: imx8m: Enable OCOTP clock before reading the registerXiaolei Wang
Commit 7d981405d0fd ("soc: imx8m: change to use platform driver") ever removed the dependency on bootloader for enabling OCOTP clock. It helped to fix a kexec kernel hang issue. But unfortunately it caused a regression on CAAM driver and got reverted. This is the second try to enable the OCOTP clock by directly calling clock API instead of indirectly enabling the clock via nvmem API. Fixes: ac34de14ac30 ("Revert "soc: imx8m: change to use platform driver"") Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-11soc/tegra: cbb: Check firewall before enabling error reportingSumit Gupta
To enable error reporting for a fabric to CCPLEX, we need to write its register for enabling error interrupt to CCPLEX during boot and later clear the error status register after error occurs. If a fabric's registers are protected and not accessible from CCPLEX, then accessing the registers will cause CBB firewall error. Add support to check whether write access from CCPLEX to the registers of a fabric is not blocked by it's firewall before enabling error reporting to CCPLEX for that fabric. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Add checks for potential out of bound errorsSumit Gupta
Added checks to avoid potential out of bounds errors which can happen if the 'slave map' and 'CBB errors' arrays are not correct or latest where some entries are missing. Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Update slave maps for Tegra234Sumit Gupta
Updating the slave map for fabrics and using the same maps for DCE, RCE and SCE as they all are a replica in Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194Sumit Gupta
In Tegra194 SoC, master_id bit range is different between cluster NOC and CBB NOC. Currently same bit range is used which results in wrong master_id value. Due to this, illegal accesses from the CCPLEX master do not result in a crash as expected. Fix this by using the correct range for the CBB NOC. Finally, it is only necessary to extract the master_id when the erd_mask_inband_err flag is set because when this is not set, a crash is always triggered. Fixes: b71344221466 ("soc/tegra: cbb: Add CBB 1.0 driver for Tegra194") Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0") Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-11soc/tegra: fuse: Use platform info with SoC revisionKartik
Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeupMaulik Shah
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Save base address of drvMaulik Shah
Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org
2022-11-09soc: qcom: rpmh-rsc: Attach RSC to cluster PM domainLina Iyer
RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org
2022-11-10soc/tegra: pmc: Process wake events during resumePetlozu Pravareshwar
During system resume, translate tier2 SC7 wake sources back into IRQs and do generic_handle_irq() to invoke the interrupt handlers for edge triggered wake events such as SW-wake. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Fix dual edge triggered wakesPetlozu Pravareshwar
When a wake event is defined to be triggered on both positive and negative edge of the input wake signal, it is crucial to know the current state of the signal when going into suspend. The intended way to obtain the current state of the wake signals is to read the WAKE_AOWAKE_SW_STATUS register, which should contains the raw state of the wake signals. However, this register is edge triggered, an edge will not be generated for signals that are already asserted prior to the assertion of WAKE_LATCH_SW. To workaround this, change the polarity of the wake level from '0' to '1' while latching the signals, as this will generate an edge for signals that are set to '1'. Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-10soc/tegra: pmc: Add I/O pad table for Tegra234Petlozu Pravareshwar
Add I/O pad table for Tegra234 to allow configuring DPD mode and switching the pins to 1.8V or 3.3V as needed. On Tegra234, DPD registers are reorganized such that there is a DPD_REQ register and a DPD_STATUS register per pad group. Update the PMC driver accordingly. While at it, use the generated tables from tegra-pinmux-scripts to make the formatting of these tables more consistent. Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> [treding@nvidia.com: generate tables from tegra-pinmux-scripts] Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()Yang Yingliang
The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-09soc: sifive: ccache: fix missing free_irq() in error path in ↵Yang Yingliang
sifive_ccache_init() Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-15 06:37:38 +0000