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2022-02-10clk: qcom: ipq8074: fix PCI-E clock oopsRobert Marko
Fix PCI-E clock related kernel oops that are caused by a missing clock parent. pcie0_rchng_clk_src has num_parents set to 2 but only one parent is actually set via parent_hws, it should also have "XO" defined. This will cause the kernel to panic on a NULL pointer in clk_core_get_parent_by_index(). So, to fix this utilize clk_parent_data to provide gcc_xo_gpll0 parent data. Since there is already an existing static const char * const gcc_xo_gpll0[] used to provide the same parents via parent_names convert those users to clk_parent_data as well. Without this earlycon is needed to even catch the OOPS as it will reset the board before serial is initialized with the following: [ 0.232279] Unable to handle kernel paging request at virtual address 0000a00000000000 [ 0.232322] Mem abort info: [ 0.239094] ESR = 0x96000004 [ 0.241778] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.244908] SET = 0, FnV = 0 [ 0.250377] EA = 0, S1PTW = 0 [ 0.253236] FSC = 0x04: level 0 translation fault [ 0.256277] Data abort info: [ 0.261141] ISV = 0, ISS = 0x00000004 [ 0.264262] CM = 0, WnR = 0 [ 0.267820] [0000a00000000000] address between user and kernel address ranges [ 0.270954] Internal error: Oops: 96000004 [#1] SMP [ 0.278067] Modules linked in: [ 0.282751] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.10 #0 [ 0.285882] Hardware name: Xiaomi AX3600 (DT) [ 0.292043] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.296299] pc : clk_core_get_parent_by_index+0x68/0xec [ 0.303067] lr : __clk_register+0x1d8/0x820 [ 0.308273] sp : ffffffc01111b7d0 [ 0.312438] x29: ffffffc01111b7d0 x28: 0000000000000000 x27: 0000000000000040 [ 0.315919] x26: 0000000000000002 x25: 0000000000000000 x24: ffffff8000308800 [ 0.323037] x23: ffffff8000308850 x22: ffffff8000308880 x21: ffffff8000308828 [ 0.330155] x20: 0000000000000028 x19: ffffff8000309700 x18: 0000000000000020 [ 0.337272] x17: 000000005cc86990 x16: 0000000000000004 x15: ffffff80001d9d0a [ 0.344391] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000006 [ 0.351508] x11: 0000000000000003 x10: 0101010101010101 x9 : 0000000000000000 [ 0.358626] x8 : 7f7f7f7f7f7f7f7f x7 : 6468626f5e626266 x6 : 17000a3a403c1b06 [ 0.365744] x5 : 061b3c403a0a0017 x4 : 0000000000000000 x3 : 0000000000000001 [ 0.372863] x2 : 0000a00000000000 x1 : 0000000000000001 x0 : ffffff8000309700 [ 0.379982] Call trace: [ 0.387091] clk_core_get_parent_by_index+0x68/0xec [ 0.389351] __clk_register+0x1d8/0x820 [ 0.394210] devm_clk_hw_register+0x5c/0xe0 [ 0.398030] devm_clk_register_regmap+0x44/0x8c [ 0.402198] qcom_cc_really_probe+0x17c/0x1d0 [ 0.406711] qcom_cc_probe+0x34/0x44 [ 0.411224] gcc_ipq8074_probe+0x18/0x30 [ 0.414869] platform_probe+0x68/0xe0 [ 0.418776] really_probe.part.0+0x9c/0x30c [ 0.422336] __driver_probe_device+0x98/0x144 [ 0.426329] driver_probe_device+0x44/0x11c [ 0.430842] __device_attach_driver+0xb4/0x120 [ 0.434836] bus_for_each_drv+0x68/0xb0 [ 0.439349] __device_attach+0xb0/0x170 [ 0.443081] device_initial_probe+0x14/0x20 [ 0.446901] bus_probe_device+0x9c/0xa4 [ 0.451067] device_add+0x35c/0x834 [ 0.454886] of_device_add+0x54/0x64 [ 0.458360] of_platform_device_create_pdata+0xc0/0x100 [ 0.462181] of_platform_bus_create+0x114/0x370 [ 0.467128] of_platform_bus_create+0x15c/0x370 [ 0.471641] of_platform_populate+0x50/0xcc [ 0.476155] of_platform_default_populate_init+0xa8/0xc8 [ 0.480324] do_one_initcall+0x50/0x1b0 [ 0.485877] kernel_init_freeable+0x234/0x29c [ 0.489436] kernel_init+0x24/0x120 [ 0.493948] ret_from_fork+0x10/0x20 [ 0.497253] Code: d50323bf d65f03c0 f94002a2 b4000302 (f9400042) [ 0.501079] ---[ end trace 4ca7e1129da2abce ]--- Fixes: f0cfcf1a ("clk: qcom: ipq8074: Add missing clocks for pcie") Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211220114119.465247-1-robimarko@gmail.com
2022-02-10clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das
The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-09spi: make remove callback a void functionUwe Kleine-König
The value returned by an spi driver's remove function is mostly ignored. (Only an error message is printed if the value is non-zero that the error is ignored.) So change the prototype of the remove function to return no value. This way driver authors are not tempted to assume that passing an error to the upper layer is a good idea. All drivers are adapted accordingly. There is no intended change of behaviour, all callbacks were prepared to return 0 before. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Jérôme Pouiller <jerome.pouiller@silabs.com> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Claudius Heine <ch@denx.de> Acked-by: Stefan Schmidt <stefan@datenfreihafen.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Acked-by: Marcus Folkesson <marcus.folkesson@gmail.com> Acked-by: Łukasz Stelmach <l.stelmach@samsung.com> Acked-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220123175201.34839-6-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-08clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568Sascha Hauer
On the rk3568 we have this (simplified) situation: .--------. .-----. .---------. -| hpll |--.--| /n |----|dclk_vop0|- `--------´ | `-----´ `---------´ | .-----. .---------. `--| /m |----|dclk_vop1|- | `-----´ `---------´ | .---------. `-------------|hdmi_ref |- `---------´ For the HDMI to work the HDMI reference clock needs to be the same as the pixel clock which means the dividers have be set to one. The last patch removed the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not changed on pixel clock changes. In order to allow the HDMI controller to set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the HDMI reference clock. With this the flow becomes: 1) HDMI controller driver sets the rate to its pixel clock which means hpll is set to the pixel clock 2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change the hpll clock anymore this means only the divider is adjusted to the desired value of dividing by one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-08clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568Sascha Hauer
The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or cpll. gpll and cpll also drive many other clocks, so changing the dclk_vop[012] clocks could change these other clocks as well. Drop CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can only adjust the pixel clocks with the divider between the PLL and the dclk_vop[012] which means the user may have to adjust the PLL clock to a suitable rate using the assigned-clock-rate device tree property. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220126145549.617165-25-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-08clk: rockchip: Add more PLL rates for rk3568Sascha Hauer
This adds a few more PLL settings needed for some standard resolutions: 297MHz 3840x2160-30.00 241.5MHz 2560x1440-59.95 135MHz 1280x1024-75.02 119MHz 1680x1050-59.88 108MHz 1280x1024-60.02 78.75MHz 1024x768-75.03 Changes since v3: - new patch Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-01clk: samsung: fix missing Tesla FSD dependency on ExynosKrzysztof Kozlowski
The Tesla FSD clock controller driver uses shared parts from Exynos ARM64 clock drivers, so add proper dependency to fix COMPILE_TEST build errors like: /usr/bin/aarch64-linux-gnu-ld: drivers/clk/samsung/clk-fsd.o: in function `fsd_cmu_probe': clk-fsd.c:(.init.text+0x9c): undefined reference to `exynos_arm64_register_cmu' Reported-by: kernel test robot <lkp@intel.com> Fixes: e3f3dc3810d3 ("clk: samsung: fsd: Add cmu_peric block clock information") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220129173407.278591-1-krzysztof.kozlowski@canonical.com
2022-01-29clk: imx: Add imx8dxl clk driverJacky Bai
Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1639747533-9778-1-git-send-email-abel.vesa@nxp.com
2022-01-29clk: imx: Add initial support for i.MXRT1050 clock driverJesse Taube
Add clock driver support for i.MXRT1050. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Suggested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220111215415.2075257-6-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-01-26clk: samsung: fsd: Add cam_csi block clock informationAlim Akhtar
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work. Cc: linux-fsd@tesla.com Signed-off-by: Sathyakam M <sathya@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-11-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add cmu_mfc block clock informationAlim Akhtar
Adds cmu_mfc clock related code, these clocks are required for MFC IP. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy <smitha.t@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-10-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add cmu_imem block clock informationAlim Akhtar
Adds cmu_imem clock related code, imem block contains IPs like WDT, DMA, TMU etc, these clocks are required for such IP function. Cc: linux-fsd@tesla.com Signed-off-by: Arjun K V <arjun.kv@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tauseef Nomani <tauseef.n@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-9-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add cmu_fsys1 clock informationAlim Akhtar
Adds cmu_fsys1 block clock information which are needed for PCIe IPs in block FSYS1. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-8-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add cmu_fsys0 clock informationAlim Akhtar
CMU_FSYS0 block has IPs like UFS, EQOS, PCIe etc, lets add the related clock information for the same. Cc: linux-fsd@tesla.com Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-7-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add cmu_peric block clock informationAlim Akhtar
Add CMU_PERIC block clock information needed for various IPs functions found in this block. Cc: linux-fsd@tesla.com Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com> Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com> Signed-off-by: Chandrasekar R <rcsekar@samsung.com> Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Sriranjani P <sriranjani.p@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-6-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-26clk: samsung: fsd: Add initial clock supportAlim Akhtar
Add initial clock support for FSD (Full Self-Driving) SoC which is required to bring-up platforms based on this SoC. Cc: linux-fsd@tesla.com Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-5-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-25clk: cs2000-cp: convert driver to regmapDaniel Mack
Regmap gives us caching, debugging infrastructure and other things for free and does away with open-coded bit-fiddling implementations. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-10-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25clk: cs2000-cp: freeze config during register fiddlingDaniel Mack
Make sure to freeze the configuration of the chip during the programming of 32-bit registers. This avoids the processing of invalid intermediate states. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-9-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25clk: cs2000-cp: make clock skip setting configurableDaniel Mack
The clock skip function of this chip is not necessarily desirable in all hardware appliances. This patch makes the feature configurable through a device-tree property. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-8-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25clk: cs2000-cp: add support for dynamic modeDaniel Mack
The CS2000 chip features two input clocks, REF_CLK and CLK_IN. In static mode, the output clock (CLK_OUT) is directly derived from REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the digital PLL. In dynamic mode, a low-frequency ratio configuration that uses a higher multiplier factor. Until now, only the static mode and high-frequency divider rations of the hardware was supported by the driver. This patch adds support for dynamic mode and both ratios: * Parse a new OF property 'cirrus,dynamic-mode' to determine the mode * In dynamic mode, present CLK_IN as parent clock, else use REF_CLK * The low-frequency ratio mode is automatically selected, depending on the mode of operation and the given input and output rates Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-25clk: cs2000-cp: Make aux output function controllableDaniel Mack
The aux output pin can be configured to output either of the two clock inputs, the generated clock or the pll lock status. Allow access to this feature through a new optional device-tree property. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-6-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: gate: Add some kunit test suitesStephen Boyd
Test various parts of the clk gate implementation with the kunit testing framework. Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Acked-by: Daniel Latypov <dlatypov@google.com> Cc: <kunit-dev@googlegroups.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220120175902.2165958-1-sboyd@kernel.org
2022-01-24clk: zynqmp: replace warn_once with pr_debug for failed clock opsMichael Tretter
The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: stm32mp1: Add parent_data to ETHRX clockMarek Vasut
Pass parent_data to ETHRX clock with new fw_name = "ETH_RX_CLK/ETH_REF_CLK". By default, this change has no impact on the operation of the clock driver. However, due to the fw_name, it permits DT to override ETHRX clock parent, which might be needed in case the ETHRX clock are supplied by external clock source. Example of MCO2 supplying clock to ETH_RX_CLK via external pad-to-pad wire: &rcc { clocks = <&rcc CK_MCO2>; clock-names = "ETH_RX_CLK/ETH_REF_CLK"; }; Note that while this patch permits to implement this rare usecase, the issue with ethernet RX and TX input clock modeling on MP1 is far more complex and requires more core plumbing. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Christophe Roullier <christophe.roullier@foss.st.com> Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20220118202958.1840431-2-marex@denx.de Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clockMarek Vasut
The ETHCK_K are modeled as composite clock of MUX and GATE, however per STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet, ETHPTPDIV divider is attached past the ETHCK_K mux, and ETH_CLK/eth_clk_fb clock are output past ETHCKEN gate. Therefore, in case ETH_CLK/eth_clk_fb are not in use AND PTP clock are in use, ETHCKEN gate can be turned off. Current driver does not permit that, fix it. This patch converts ETHCK_K from composite clock into a ETHCKEN gate, ETHPTP_K from composite clock into ETHPTPDIV divider, and adds another NO_ID clock "ck_ker_eth" which models the ETHSRC mux and is parent clock to both ETHCK_K and ETHPTP_K. Therefore, all references to ETHCK_K and ETHPTP_K remain functional as before. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Christophe Roullier <christophe.roullier@foss.st.com> Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20220118202958.1840431-1-marex@denx.de Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus
MCK1 feeds the External Bus Interface (EBI). EBI's clock rate is used to translate EBI's timmings to SMC timings, thus we need to handle MCK1 in the EBI driver. Allow MCK1 to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220111125310.902856-1-tudor.ambarus@microchip.com Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI
Make AUDIOPINCK accessible via phandle to select it as peripheral clock parent using assigned-clock-parents in DT where available. Signed-off-by: Zixun LI <admin@hifiphile.com> Reviewed-by: Claudiu Beznea <Claudiu.Beznea@microchip.com> Link: https://lore.kernel.org/r/20220111142051.37957-1-admin@hifiphile.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: mediatek: Fix memory leaks on probeJosé Expósito
Handle the error branches to free memory where required. Addresses-Coverity-ID: 1491825 ("Resource leak") Signed-off-by: José Expósito <jose.exposito89@gmail.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20220115183059.GA10809@elementary Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk-si5341: replace snprintf in show functions with sysfs_emitQing Wang
coccicheck complains about the use of snprintf() in sysfs show functions. Fix the following coccicheck warning: drivers/clk/clk-si5341.c:1471: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1486: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1501: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1516: WARNING: use scnprintf or sprintf. Use sysfs_emit instead of scnprintf or sprintf makes more sense. Signed-off-by: Qing Wang <wangqing@vivo.com> Link: https://lore.kernel.org/r/1634280331-4150-1-git-send-email-wangqing@vivo.com Reviewed-by: Robert Hancock <robert.hancock@calian.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: si5341: fix reported clk_rate when output divider is 2Adam Wujek
SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2 is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set, SI5341_OUT_R_REG is set 0). Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was interpreted as output is disabled. Signed-off-by: Adam Wujek <dev_public@wujek.eu> Link: https://lore.kernel.org/r/20211203141125.2447520-1-dev_public@wujek.eu Reviewed-by: Robert Hancock <robert.hancock@calian.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht
Adds "canfd0" to mod clocks. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20220111162231.10390-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar
As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600 MHz, but with current multiplier and divider values this resulted to 1596 MHz. This patch updates the multiplier and divider values for PLL2 and PLL3 so that we get the exact (1600 MHz) values. Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC") Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko
Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs. Similar to other R-Car Gen3 SoC, exact information on the parents of MLP clocks on E3 and D3 is not available. However, since the parents of these clocks are not anyhow software-controllable, the only harm from this is inexact information exported via debugfs. So just keep the parent set in the same way as with other Gen3 SoCs. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda
Add SYS-DMAC clocks on r8a779f0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211221052423.597283-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-21Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "Some hot fixes for clk driver patches merged last week and one oops fix: - Fix license on recent MediaTek drivers - Initialize a variable before use in the new Visconti driver - Avoid an oops by unregistering the clk provider in si5341" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: mediatek: relicense mt7986 clock driver to GPL-2.0 clk: visconti: Fix uninitialized variable in printk clk: si5341: Fix clock HW provider cleanup
2022-01-19clk: mediatek: relicense mt7986 clock driver to GPL-2.0Sam Shih
The previous mt7986 clock drivers were incorrectly marked as GPL-1.0. This patch changes the driver to the standard GPL-2.0 license. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Link: https://lore.kernel.org/r/20220119123658.10095-2-sam.shih@mediatek.com Reported-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-13clk: visconti: Fix uninitialized variable in printkDan Carpenter
The "pll_clck" variable is uninitialized. The "ret" error code was supposed to be printed instead. Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220111072529.GJ11243@kili Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-13clk: si5341: Fix clock HW provider cleanupRobert Hancock
The call to of_clk_add_hw_provider was not undone on remove or on probe failure, which could cause an oops on a subsequent attempt to retrieve clocks for the removed device. Switch to the devm version of the function to avoid this issue. Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20220112203816.1784610-1-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have a couple patches in the framework core this time around but they're mostly minor cleanups and some debugfs stuff. The real work that's in here is the typical pile of clk driver updates and new SoC support. Per usual (or maybe just recent trends), Qualcomm gains a handful of SoC drivers additions and has the largest diffstat. After that there are quite a few updates to the Allwinner (sunxi) drivers to support modular drivers and Renesas is heavily updated to add more support for various clks. Overall it looks pretty normal. New Drivers: - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support - Clock and reset driver for Toshiba Visconti SoCs - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) - Allwinner D1 clks - Lan966x Generic Clock Controller driver and associated DT bindings - Qualcomm SDX65, SM8450, and MSM8976 GCC clks - Qualcomm SDX65 and SM8450 RPMh clks Updates: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all i.MX drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - Refactoring of the CPU clocks registration to use common interface - An update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - Prep for runtime PM and generic power domains on Tegra - Support modular Allwinner clk drivers via platform bus - Lan966x clock driver extended to support clock gating - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on Renesas RZ/G2L - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Add clk-provider.h to various Qualcomm clk drivers - devm version of clk_hw_register_gate() - kerneldoc fixes in a couple drivers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits) clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver ...
2022-01-11Merge branches 'clk-ingenic' and 'clk-mediatek' into clk-nextStephen Boyd
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support * clk-ingenic: clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks * clk-mediatek: clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
2022-01-11Merge branches 'clk-socfpga', 'clk-toshiba', 'clk-st' and 'clk-bitmain' into ↵Stephen Boyd
clk-next - Clock and reset driver for Toshiba Visconti SoCs * clk-socfpga: clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: remove redundant assignment after a mask operation clk: socfpga: remove redundant assignment on division * clk-toshiba: clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC * clk-st: clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent * clk-bitmain: clk: bm1880: remove kfrees on static allocations
2022-01-11Merge branches 'clk-nvidia', 'clk-imx', 'clk-samsung' and 'clk-qcom' into ↵Stephen Boyd
clk-next * clk-nvidia: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114 * clk-imx: clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true * clk-samsung: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks * clk-qcom: (25 commits) clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock ...
2022-01-11Merge branches 'clk-x86', 'clk-stm', 'clk-amlogic' and 'clk-allwinner' into ↵Stephen Boyd
clk-next * clk-x86: clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: Introduce clk-tps68470 driver platform/x86: int3472: Deal with probe ordering issues platform/x86: int3472: Pass tps68470_regulator_platform_data to the tps68470-regulator MFD-cell platform/x86: int3472: Pass tps68470_clk_platform_data to the tps68470-regulator MFD-cell platform/x86: int3472: Add get_sensor_adev_and_name() helper platform/x86: int3472: Split into 2 drivers platform_data: Add linux/platform_data/tps68470.h file i2c: acpi: Add i2c_acpi_new_device_by_fwnode() function i2c: acpi: Use acpi_dev_ready_for_enumeration() helper ACPI: delay enumeration of devices with a _DEP pointing to an INT3472 device * clk-stm: clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after system enter shell * clk-amlogic: clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB * clk-allwinner: clk: sunxi-ng: Add support for the D1 SoC clocks clk: sunxi-ng: gate: Add macros for gates with fixed dividers clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hw clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw dt-bindings: clk: Add compatibles for D1 CCUs clk: sunxi-ng: Allow the CCU core to be built as a module clk: sunxi-ng: Convert early providers to platform drivers clk: sunxi-ng: Allow drivers to be built as modules clk: sunxi-ng: Export symbols used by CCU drivers
2022-01-11Merge branches 'clk-doc', 'clk-renesas', 'clk-at91', 'clk-cleanup' and ↵Stephen Boyd
'clk-debugfs' into clk-next * clk-doc: clk: Gemini: fix struct name in kernel-doc clk: zynq: pll: Fix kernel-doc warnings clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1 * clk-renesas: (31 commits) clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions clk: renesas: r9a07g044: Add TSU clock and reset entry mmc: renesas_sdhi: Simplify an expression mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0 clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple() clk: renesas: cpg-mssr: Check return value of pm_genpd_init() clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple() clk: renesas: rzg2l: Check return value of pm_genpd_init() clk: renesas: r9a07g044: Add RSPI clock and reset entries clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV clk: renesas: rzg2l: Add CPG_PL1_DDIV macro mmc: renesas_sdhi: Parse DT for SDnH mmc: renesas_sdhi: Use dev_err_probe when getting clock fails ... * clk-at91: clk: lan966x: Extend lan966x clock driver for clock gating support dt-bindings: clock: lan966x: Extend includes with clock gates dt-bindings: clock: lan966x: Extend for clock gate support clk: gate: Add devm_clk_hw_register_gate() clk: lan966x: Add lan966x SoC clock driver dt-bindings: clock: lan966x: Add LAN966X Clock Controller dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs * clk-cleanup: clk: stm32mp1: remove redundant assignment to pointer data clk: __clk_core_init() never takes NULL clk: clk_core_get() can also return NULL clk/ti/adpll: Make const pointer error a static const array * clk-debugfs: clk: Enable/Disable runtime PM for clk_summary clk: Emit a stern warning with writable debugfs enabled clk: Add write operation for clk_parent debugfs node
2022-01-10Merge tag 'drm-next-2022-01-07' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm updates from Dave Airlie: "Highlights are support for privacy screens found in new laptops, a bunch of nomodeset refactoring, and i915 enables ADL-P systems by default, while starting to add RPL-S support. vmwgfx adds GEM and support for OpenGL 4.3 features in userspace. Lots of internal refactorings around dma reservations, and lots of driver refactoring as well. Summary: core: - add privacy screen support - move nomodeset option into drm subsystem - clean up nomodeset handling in drivers - make drm_irq.c legacy - fix stack_depot name conflicts - remove DMA_BUF_SET_NAME ioctl restrictions - sysfs: send hotplug event - replace several DRM_* logging macros with drm_* - move hashtable to legacy code - add error return from gem_create_object - cma-helper: improve interfaces, drop CONFIG_DRM_KMS_CMA_HELPER - kernel.h related include cleanups - support XRGB2101010 source buffers ttm: - don't include drm hashtable - stop pruning fences after wait - documentation updates dma-buf: - add dma_resv selftest - add debugfs helpers - remove dma_resv_get_excl_unlocked - documentation - make fences mandatory in dma_resv_add_excl_fence dp: - add link training delay helpers gem: - link shmem/cma helpers into separate modules - use dma_resv iteratior - import dma-buf namespace into gem helper modules scheduler: - fence grab fix - lockdep fixes bridge: - switch to managed MIPI DSI helpers - register and attach during probe fixes - convert to YAML in several places. panel: - add bunch of new panesl simpledrm: - support FB_DAMAGE_CLIPS - support virtual screen sizes - add Apple M1 support amdgpu: - enable seamless boot for DCN 3.01 - runtime PM fixes - use drm_kms_helper_connector_hotplug_event - get all fences at once - use generic drm fb helpers - PSR/DPCD/LTTPR/DSC/PM/RAS/OLED/SRIOV fixes - add smart trace buffer (STB) for supported GPUs - display debugfs entries - new SMU debug option - Documentation update amdkfd: - IP discovery enumeration refactor - interface between driver fixes - SVM fixes - kfd uapi header to define some sysfs bitfields. i915: - support VESA panel backlights - enable ADL-P by default - add eDP privacy screen support - add Raptor Lake S (RPL-S) support - DG2 page table support - lots of GuC/HuC fw refactoring - refactored i915->gt interfaces - CD clock squashing support - enable 10-bit gamma support - update ADL-P DMC fw to v2.14 - enable runtime PM autosuspend by default - ADL-P DSI support - per-lane DP drive settings for ICL+ - add support for pipe C/D DMC firmware - Atomic gamma LUT updates - remove CCS FB stride restrictions on ADL-P - VRR platform support for display 11 - add support for display audio codec keepalive - lots of display refactoring - fix runtime PM handling during PXP suspend - improved eviction performance with async TTM moves - async VMA unbinding improvements - VMA locking refactoring - improved error capture robustness - use per device iommu checks - drop bits stealing from i915_sw_fence function ptr - remove dma_resv_prune - add IC cache invalidation on DG2 nouveau: - crc fixes - validate LUTs in atomic check - set HDMI AVI RGB quant to full tegra: - buffer objects reworks for dma-buf compat - NVDEC driver uAPI support - power management improvements etnaviv: - IOMMU enabled system support - fix > 4GB command buffer mapping - close a DoS vector - fix spurious GPU resets ast: - fix i2c initialization rcar-du: - DSI output support exynos: - replace legacy gpio interface - implement generic GEM object mmap msm: - dpu plane state cleanup in prep for multirect - dpu debugfs cleanups - dp support for sc7280 - a506 support - removal of struct_mutex - remove old eDP sub-driver anx7625: - support MIPI DSI input - support HDMI audio - fix reading EDID lvds: - fix bridge DT bindings megachips: - probe both bridges before registering dw-hdmi: - allow interlace on bridge ps8640: - enable runtime PM - support aux-bus tx358768: - enable reference clock - add pulse mode support ti-sn65dsi86: - use regmap bulk write - add PWM support etnaviv: - get all fences at once gma500: - gem object cleanups kmb: - enable fb console radeon: - use dma_resv_wait_timeout rockchip: - add DSP hold timeout - suspend/resume fixes - PLL clock fixes - implement mmap in GEM object functions - use generic fbdev emulation sun4i: - use CMA helpers without vmap support vc4: - fix HDMI-CEC hang with display is off - power on HDMI controller while disabling - support 4K@60Hz modes - support 10-bit YUV 4:2:0 output vmwgfx: - fix leak on probe errors - fail probing on broken hosts - new placement for MOB page tables - hide internal BOs from userspace - implement GEM support - implement GL 4.3 support virtio: - overflow fixes xen: - implement mmap as GEM object function omapdrm: - fix scatterlist export - support virtual planes mediatek: - MT8192 support - CMDQ refinement" * tag 'drm-next-2022-01-07' of git://anongit.freedesktop.org/drm/drm: (1241 commits) drm/amdgpu: no DC support for headless chips drm/amd/display: fix dereference before NULL check drm/amdgpu: always reset the asic in suspend (v2) drm/amdgpu: put SMU into proper state on runpm suspending for BOCO capable platform drm/amd/display: Fix the uninitialized variable in enable_stream_features() drm/amdgpu: fix runpm documentation amdgpu/pm: Make sysfs pm attributes as read-only for VFs drm/amdgpu: save error count in RAS poison handler drm/amdgpu: drop redundant semicolon drm/amd/display: get and restore link res map drm/amd/display: support dynamic HPO DP link encoder allocation drm/amd/display: access hpo dp link encoder only through link resource drm/amd/display: populate link res in both detection and validation drm/amd/display: define link res and make it accessible to all link interfaces drm/amd/display: 3.2.167 drm/amd/display: [FW Promotion] Release 0.0.98 drm/amd/display: Undo ODM combine drm/amd/display: Add reg defs for DCN303 drm/amd/display: Changed pipe split policy to allow for multi-display pipe split drm/amd/display: Set optimize_pwr_state for DCN31 ...
2022-01-10Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull RISC-V SoC updates from Arnd Bergmann: "Add support for StarFive JH7100 RISC-V SoC This adds support for the StarFive JH7100, including the necessary device drivers and DT files for the BeagleV Starlight prototype board, with additional boards to be added later. This SoC promises to be the first usable low-cost platform for RISC-V. I've taken this through the SoC tree in the anticipation of adding a few other Arm based SoCs as well, but those did not pass the review in time, so it's only this one" * tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: reset: starfive-jh7100: Fix 32bit compilation RISC-V: Add BeagleV Starlight Beta device tree RISC-V: Add initial StarFive JH7100 device tree serial: 8250_dw: Add StarFive JH7100 quirk dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts pinctrl: starfive: Add pinctrl driver for StarFive SoCs dt-bindings: pinctrl: Add StarFive JH7100 bindings dt-bindings: pinctrl: Add StarFive pinctrl definitions reset: starfive-jh7100: Add StarFive JH7100 reset driver dt-bindings: reset: Add Starfive JH7100 reset bindings dt-bindings: reset: Add StarFive JH7100 reset definitions clk: starfive: Add JH7100 clock generator driver dt-bindings: clock: starfive: Add JH7100 bindings dt-bindings: clock: starfive: Add JH7100 clock definitions dt-bindings: interrupt-controller: Add StarFive JH7100 plic dt-bindings: timer: Add StarFive JH7100 clint RISC-V: Add StarFive SoC Kconfig option
2022-01-10Merge tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC devicetree updates from Arnd Bergmann: "As usual, this is the bulk of the updates for the SoC tree, adding more devices to existing files, addressing issues from ever improving automated checking, and fixing minor issues. The most interesting bits as usual are the new platforms. All the newly supported SoCs belong into existing families this time: - Qualcomm gets support for two newly announced platforms, both of which can now work in production environments: the SDX65 5G modem that can run a minimal Linux on its Cortex-A7 core, and the Snapdragon 8 Gen 1, their latest high-end phone SoC. - Renesas adds support for R-Car S4-8, the most recent automotive Server/Communication SoC. - TI adds support for J721s2, a new automotive SoC in the K3 family. - Mediatek MT7986a/b is a SoC used in Wifi routers, the latest generation following their popular MT76xx series. Only basic support is added for now. - NXP i.MX8 ULP8 is a new low-power variant of the widespread i.MX8 series. - TI SPEAr320s is a minor variant of the old SPEAr320 SoC that we have supported for a long time. New boards with the existing SoCs include - Aspeed AST2500/AST2600 BMCs in TYAN, Facebook and Yadro servers - AT91/SAMA5 based evaluation board - NXP gains twenty new development and industrial boards for their i.MX and Layerscape SoCs - Intel IXP4xx now supports the final two machines in device tree that were previously only supported in old style board files. - Mediatek MT6589 is used in the Fairphone FP1 phone from 2013, while MT8183 is used in the Acer Chromebook 314. - Qualcomm gains support for the reference machines using the two new SoCs, plus a number of Chromebook variants and phones based on the Snapdragon 7c, 845 and 888 SoCs, including various Sony Xperia devices and the Microsoft Surface Duo 2. - ST STM32 now supports the Engicam i.Core STM32MP1 carrier board. - Tegra now boots various older Android devices based on 32-bit chips out of the box, including a number of ASUS Transformer tablets. There is also a new Jetson AGX Orin developer kit. - Apple support adds the missing device trees for all the remaining M1 Macbook and iMac variants, though not yet the M1 Pro/Max versions. - Allwinner now supports another version of the Tanix TX6 set-top box based on the H6 SoC. - Broadcom gains support for the Netgear RAXE500 Wireless router based on BCM4908" * tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (574 commits) Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U" arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX arm64: dts: qcom: sm8450-qrd: Enable USB nodes arm64: dts: qcom: sm8450: Add usb nodes ARM: dts: aspeed: add LCLK setting into LPC KCS nodes dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property ARM: dts: aspeed: add LCLK setting into LPC IBT node ARM: dts: aspeed: p10: Add TPM device ARM: dts: aspeed: p10: Enable USB host ports ARM: dts: aspeed: Add TYAN S8036 BMC machine ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config ARM: dts: aspeed: Adding Facebook Bletchley BMC ARM: dts: aspeed: g220a: Enable secondary flash ARM: dts: Add openbmc-flash-layout-64-alt.dtsi ARM: dts: aspeed: Add secure boot controller node dt-bindings: aspeed: Add Secure Boot Controller bindings ARM: dts: Remove "spidev" nodes dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850 dt-bindings: arm: samsung: Document E850-96 board binding dt-bindings: Add vendor prefix for WinLink ...
2022-01-07clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()Nathan Chancellor
Clang warns: drivers/clk/visconti/pll.c:292:20: warning: address of array 'ctx->clk_data.hws' will always evaluate to 'true' [-Wpointer-bool-conversion] if (ctx->clk_data.hws && id) ~~~~~~~~~~~~~~^~~ ~~ 1 warning generated. This array cannot be NULL if ctx is not NULL, which is allocated in visconti_init_pll(), so just remove the check, which matches other clk drivers. Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1564 Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20220107183303.2337676-1-nathan@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-06clk: mediatek: add mt7986 clock supportSam Shih
Add MT7986 clock support, include topckgen, apmixedsys, infracfg, and ethernet subsystem clocks. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Link: https://lore.kernel.org/r/20211217121148.6753-4-sam.shih@mediatek.com Reviewed-by: Ryder Lee <ryder.lee@kernel.org> [sboyd@kernel.org: Fix typos in Kconfig, there are more existing typos from where they were copied from of but whatever] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-06clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpersAngeloGioacchino Del Regno
Appropriately change calls to regmap_update_bits() with regmap_set_bits() and regmap_clear_bits() for improved readability. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220103143712.46675-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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