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2025-08-11arm64: dts: qcom: x1e80100: add empty mdss_dp3_out endpointDmitry Baryshkov
Follow the example of other DP controllers and also eDP controller on SC7280 and move mdss_dp3_out endpoint declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-3-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc8280xp: add empty mdss*_dp*_out endpointsDmitry Baryshkov
Follow the example of other DP controllers and also eDP controller on SC7280 and move all mdss[01]_dp[0123]_out endpoints declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-2-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc8180x: add empty mdss_edp_out endpointDmitry Baryshkov
Follow the example of other DP controllers and also eDP controller on SC7280 and move mdss_edp_out endpoint declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-1-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sa8775p: add link_down reset for pcieZiyue Zhang
SA8775p supports 'link_down' reset on hardware, so add it for both pcie0 and pcie1, which can provide a better user experience. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725102231.3608298-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sa8775p: remove aux clock from pcie phyZiyue Zhang
The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this patch uses to replace the incorrect reference. The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is typically used by the controller, while PHY_AUX_CLK is required by certain PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock gating and power management. Some non-Gen4 Qualcomm PHYs also use PHY_AUX_CLK, but they do not require AUX_CLK. This change ensures proper clock configuration and avoids unnecessary dependencies. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc7280: Flatten usb controller nodesKrishna Kurapati
Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # FP5 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250728035812.2762957-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc7280-chrome-common: Remove duplicate nodeKonrad Dybcio
sc7280.dtsi already includes the very same definition (bar 'memory@' vs 'video@', which doesn't matter). Remove the duplicate to fix a lot of dtbs W=1 warning instances (unique_unit_address_if_enabled). Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250728-topic-chrome_dt_fixup-v1-1-1fc38a95d5ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcm2290: Enable HS eMMC timing modesLoic Poulain
The host controller supports HS200/HS400 and HS400 enhanced strobe mode. On RB1, this improves Linux eMMC read speed, from ~170MB/s to 300MB/s. Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250728093426.1413379-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm6150: Add ADSP and CDSP fastrpc nodesLing Xu
Add ADSP and CDSP fastrpc nodes for SM6150 platform. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250729031259.4190916-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8650: Add ACD levels for GPUNeil Armstrong
Update GPU node to include acd level values. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250729-topic-sm8650-upstream-gpu-acd-level-v1-1-258090038a41@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcm2290: Add TCSR download mode addressSumit Garg
Allow configuration of download mode via qcom_scm driver via specifying download mode register address in the TCSR space. It is especially useful for a clean watchdog reset without entry into download mode. The problem remained un-noticed until now since error reporting for missing download mode configuration feature was explicitly suppressed. Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250730132230.247727-1-sumit.garg@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845-oneplus: Deduplicate shared entriesDavid Heidelberg
Use the definition for qcom,msm-id and put them into the common dtsi. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-2-9f44d125ee44@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845*: Use definition for msm-idDavid Heidelberg
For all boards it's QCOM_ID_SDM845 except Dragonboard, where it's QCOM_ID_SDA845. Except for OnePlus 6 / 6T, which is handled in following commit. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-1-9f44d125ee44@ixit.cz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm670-google-sargo: enable chargerRichard Acayan
The Pixel 3a has a rechargeable 3000 mAh battery. Describe it and enable its charging controller in PM660. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630224158.249726-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable HBR3 on external DPsAleksandrs Vinarskis
When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630205514.14022-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1-crd: Enable HBR3 on external DPsAleksandrs Vinarskis
When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630205514.14022-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11ARM: dts: qcom: msm8974-samsung-hlte: Add touchkey supportAdam Honse
Add support for the touchkeys on the Samsung Galaxy Note 3 (hlte). Signed-off-by: Adam Honse <calcprogrammer1@gmail.com> Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250618-hlte-touchkey-v2-1-2cf188b57e31@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11ARM: dts: qcom: pm8921: add vibrator device nodeShinjo Park
Use the same definition as pm8058.dtsi. Since vibrator is used only by some devices, disable it by default and let it be enabled explicitly. Signed-off-by: Shinjo Park <peremen@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250613194253.20080-1-peremen@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11ARM: dts: qcom: add device tree for Sony Xperia SPAntony Kurniawan Soemardi
Add initial device tree support for the Sony Xperia SP (codename: sony-huashan), a smartphone based on the Qualcomm MSM8960T SoC. There are two variants of the Xperia SP, one without LTE and one with LTE. This device tree should work for both variants, though it has only been tested on the non-LTE variant. The following are currently supported: - Serial console support via gsbi8 - GPIO keys for volume up/down buttons - PM8921 keypad with camera focus/capture keys - eMMC (sdcc1) and micro SD card (sdcc3) support - USB OTG support Other hardware features are not yet implemented. Booting notes: Booting a kernel requires using the Sony ELF boot image format, which embeds the kernel, ramdisk, RPM firmware, and cmdline. This can be created using the `mkelf` tool. For example: python2 mkelf.py -o boot.img \ kernel+dtb@0x80208000 \ ramdisk.img@0x81900000 \ RPM.bin@0x00020000,rpm \ cmdline.txt@cmdline The resulting `boot.img` can then be flashed via fastboot. A detailed guide, including an alternative method, is available at: https://wiki.postmarketos.org/wiki/Sony_Xperia_SP_(sony-huashan) Signed-off-by: Antony Kurniawan Soemardi <linux@smankusors.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-5-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Replace ↵Laurent Pinchart
clock-frequency in camera sensor node The clock-frequency for camera sensors has been deprecated in favour of the assigned-clocks and assigned-clock-rates properties. Replace it in the device tree. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250710174808.5361-13-laurent.pinchart@ideasonboard.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint readerStephan Gerhold
The X1E80100 CRD has a Goodix fingerprint reader connected to the USB multiport controller on eUSB6. All other ports (including USB super-speed pins) are unused. Set it up in the device tree together with the NXP PTN3222 repeater. Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250714-x1e80100-crd-fp-v2-1-3246eb02b679@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8450: Flatten usb controller nodeKrishna Kurapati
Flatten usb controller node and update to using latest bindings and flattened driver approach. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250715052739.3831549-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8450-qrd: add pmic glink nodeKrishna Kurapati
Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250715052739.3831549-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs8300-ride: Enable SDHC1 nodeSayali Lokhande
Enable sdhc1 support for qcs8300 ride platform. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716085125.27169-3-quic_sayalil@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs8300: Add eMMC supportSayali Lokhande
Add eMMC support for qcs8300 board. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716085125.27169-2-quic_sayalil@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: Remove sdm845-cheza boardsKonrad Dybcio
Cheza was a prototype board, used mainly by the ChromeOS folks, whose former efforts on making linux-arm-msm better we greatly appreciate. There are close to zero known-working devices at this point in time (see the link below) and it was never productized. Remove it to ease maintenance burden. Link: https://lore.kernel.org/linux-arm-msm/5567e441-055d-443a-b117-ec16b53dc059@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-1-6fa8d3261813@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8750: Add BWMONsShivnandan Kumar
Add the CPU BWMONs for SM8750 SoCs. Notably, the one related to cluster0 requires that it's mapped with the nE memory attribute. This is specific to a single instance, on this platform only and should not be mimicked elsewhere. Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com> [konrad: add nonposted-mmio where necessary, re-sort nodes] Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716-8750_cpubwmon-v4-2-12212098e90f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: sm8250-xiaomi-pipa: Update battery infoArseniy Velikanov
Added max design microvolt. Merged battery info into one node, since pmic fuel-gauge uses mixed info about dual-cell battery. Reviewed-by: Luka Panio <lukapanio@gmail.com> Signed-off-by: Arseniy Velikanov <me@adomerle.pw> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716141041.24507-3-me@adomerle.pw Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8250-xiaomi-pipa: Drop unused bq27z561Arseniy Velikanov
It looks like the fuel gauge is not connected to the battery, it reports nonsense info. Downstream kernel uses pmic fg. Reviewed-by: Luka Panio <lukapanio@gmail.com> Signed-off-by: Arseniy Velikanov <me@adomerle.pw> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716141041.24507-2-me@adomerle.pw Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8250-xiaomi-pipa: Drop nonexistent pm8009 pmicArseniy Velikanov
PM8009 was erroneously added since this device doesn't actually have it. It triggers a big critical error at boot, so we're drop it. Fixes: 264beb3cbd0d ("arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree") Reviewed-by: Luka Panio <lukapanio@gmail.com> Signed-off-by: Arseniy Velikanov <me@adomerle.pw> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250716141041.24507-1-me@adomerle.pw Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615: Set LDO12A regulator to HPM to avoid boot hangZiyue Zhang
On certain platforms (e.g., QCS615), consumers of LDO12A—such as PCIe, UFS, and eMMC—may draw more than 10mA of current during boot. This can exceed the regulator's limit in Low Power Mode (LPM), triggering current limit protection and causing the system to hang. To address this, there are two possible approaches: a) Set the regulator's initial mode to High Performance Mode (HPM) in the device tree. b) Keep the default LPM setting and have each consumer driver explicitly set its current load. Since some regulators are shared among multiple consumers, and setting the current must be coordinated across all of them, we will initially adopt option a by setting the regulator to HPM. We can later migrate to option b when the timing is appropriate and all consumer drivers are ready. Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> Link: https://lore.kernel.org/r/20250717072746.987298-1-quic_ziyuzhan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs6490-rb3gen2: Add missing clkreq pinctrl propertyKrishna Chaitanya Chundru
Add the missing clkreq pinctrl entry to the PCIe1 node. This ensures proper configuration of the CLKREQ# signal, which is needed for proper functioning of PCIe ASPM. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250717-clkreq-v1-1-5a82c7e8e891@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clockGeorge Moussalem
The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: ipq5018: Add CMN PLL nodeGeorge Moussalem
Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: Add crypto nodesGeorge Moussalem
IPQ5018 uses Qualcomm QCE crypto engine v5.1 which is already supported. So let's add the dts nodes for its DMA v1.7.4 and QCE itself. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250721-ipq5018-crypto-v3-1-b9cd9b0ef147@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: add PRNG nodeGeorge Moussalem
PRNG inside of IPQ5018 is already supported, so let's add the node for it. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250721-ipq5018-prng-v1-1-474310e0575d@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP ↵Raviteja Laggyshetty
OPP tables to scale DDR/L3 Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables required to scale DDR and L3 per freq-domain on QCS8300 platform. As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P compatible as fallback for QCS8300 EPSS device node. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250722055039.135140-2-raviteja.laggyshetty@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCPQiang Yu
Add perst, wake and clkreq sideband signals and required regulators in PCIe3 controller and PHY device tree node. Describe the voltage rails of the x8 PCI slots for PCIe3 port. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3Qiang Yu
Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11x86/fpu: Fix NULL dereference in avx512_status()Fushuai Wang
Problem ------- With CONFIG_X86_DEBUG_FPU enabled, reading /proc/[kthread]/arch_status causes a warning and a NULL pointer dereference. This is because the AVX-512 timestamp code uses x86_task_fpu() but doesn't check it for NULL. CONFIG_X86_DEBUG_FPU addles that function for kernel threads (PF_KTHREAD specifically), making it return NULL. The point of the warning was to ensure that kernel threads only access task->fpu after going through kernel_fpu_begin()/_end(). Note: all kernel tasks exposed in /proc have a valid task->fpu. Solution -------- One option is to silence the warning and check for NULL from x86_task_fpu(). However, that warning is fairly fresh and seems like a defense against misuse of the FPU state in kernel threads. Instead, stop outputting AVX-512_elapsed_ms for kernel threads altogether. The data was garbage anyway because avx512_timestamp is only updated for user threads, not kernel threads. If anyone ever wants to track kernel thread AVX-512 use, they can come back later and do it properly, separate from this bug fix. [ dhansen: mostly rewrite changelog ] Fixes: 22aafe3bcb67 ("x86/fpu: Remove init_task FPU state dependencies, add debugging warning for PF_KTHREAD tasks") Co-developed-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Fushuai Wang <wangfushuai@baidu.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20250811185044.2227268-1-sohil.mehta%40intel.com
2025-08-11PCI: Add Extended Tag + MRRS quirk for Xeon 6Ilpo Järvinen
When bifurcated to x2, Xeon 6 Root Port performance is sensitive to the configuration of Extended Tags, Max Read Request Size (MRRS), and 10-Bit Tag Requester (note: there is currently no 10-Bit Tag support in the kernel). While those can be configured to the recommended values by FW, kernel may decide to overwrite the initial values. Add a quirk that disallows enabling Extended Tags and setting MRRS larger than 128B for devices under Xeon 6 Root Ports if the Root Port is bifurcated to x2. Use the host bridge's enable_device hook to overwrite MRRS if it's set to >128B for the device to be enabled. The earlier attempts to implement this quirk polluted PCI core code with the checks necessary to support this quirk. Using the enable_device hook keeps the quirk well-contained, away from the PCI core code. Suggested-by: Lukas Wunner <lukas@wunner.de> Link: https://cdrdv2.intel.com/v1/dl/getContent/837176 Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [bhelgaas: 2x -> x2, rename quirk] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250610114802.7460-1-ilpo.jarvinen@linux.intel.com
2025-08-11arm64: dts: qcom: sm8650: Sort nodes by unit addressKrzysztof Kozlowski
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in SM8650 DTSI to fix that. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250727193652.4029-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: Add SPI nand supportGeorge Moussalem
Add QPIC SPI NAND support for IPQ5018 SoC. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250501-ipq5018-spi-qpic-snand-v1-2-31e01fbb606f@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c ↵Bartosz Golaszewski
SDA and SCL The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-3-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCLBartosz Golaszewski
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Reported-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-2-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCLBartosz Golaszewski
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Tested-by: Alexey Klimov <alexey.klimov@linaro.org> Reported-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-1-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: pmk8550: Correct gpio node nameLuca Weiss
The reg for the GPIOs is 0xb800 and not 0x8800, so fix this copy-paste mistake. Fixes: e9c0a4e48489 ("arm64: dts: qcom: Add PMK8550 pmic dtsi") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250625-pmk8550-gpio-name-v1-1-58402849f365@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615-ride: Enable WiFi/BT nodesYu Zhang(Yuriy)
Enable WiFi/BT on qcs615-ride by adding a node for the PMU module of the WCN6855 and assigning its LDO power outputs to the existing WiFi/BT module. Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250727-615-v7-2-2adb6233bbb9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615: add a PCIe port for WLANYu Zhang(Yuriy)
Add an original PCIe port for WLAN. This port will be referenced and supplemented by specific WLAN devices. Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250727-615-v7-1-2adb6233bbb9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615-ride: Enable PCIe interfaceKrishna chaitanya chundru
Add platform configurations in devicetree for PCIe, board related gpios, PMIC regulators, etc. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725112346.614316-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-30 14:58:05 +0000