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2025-08-13arm64: dts: ti: k3-am62a-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the AM62A TRM [0]. Interrupt Line | Source Interrupt ---------------------------|---------------------------------- GICSS0_COMMON_0_SPI_IN_175 | CSI_RX_IF0_COMMON_0_CSI_ERR_IRQ_0 GICSS0_COMMON_0_SPI_IN_173 | CSI_RX_IF0_COMMON_0_CSI_IRQ_0 [0]: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-8-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-am62-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the AM62 TRM [0]. Interrupt Line | Source Interrupt ---------------|-------------------------- gicss0.spi.175 | csi_rx_if.0.csi_err_irq.0 gicss0.spi.173 | csi_rx_if.0.csi_irq.0 [0]: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-7-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j722s-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J722S TRM [0]. Interrupt Line | Source Interrupt -------------------|------------------------- GICSS0_SPI_IN_178 | CSI_RX_IF1_CSI_ERR_IRQ_0 GICSS0_SPI_IN_179 | CSI_RX_IF1_CSI_IRQ_0 GICSS0_SPI_IN_219 | CSI_RX_IF2_CSI_ERR_IRQ_0 GICSS0_SPI_IN_232 | CSI_RX_IF2_CSI_IRQ_0 GICSS0_SPI_IN_249 | CSI_RX_IF3_CSI_ERR_IRQ_0 GICSS0_SPI_IN_250 | CSI_RX_IF3_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-6-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-am62p-j722s-common-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J722S TRM [0]. Interrupt Line | Source Interrupt -------------------|------------------------- GICSS0_SPI_IN_175 | CSI_RX_IF0_CSI_ERR_IRQ_0 GICSS0_SPI_IN_173 | CSI_RX_IF0_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-5-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j784s4-j742s2-main-common: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CSI2RX. Interrupt IDs are taken from the J784S4 TRM [0]. Interrupt Line | Source Interrupt --------------------|------------------------- GIC500SS_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_0 GIC500SS_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_0 GIC500SS_SPI_IN_193 | CSI_RX_IF2_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_192 | CSI_RX_IF2_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/spruj52 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-4-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721e-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CSI2RX. Interrupt IDs are taken from the J721E TRM [0]. Interrupt Line | Source Interrupt ------------------|------------------------- GIC500_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_0 GIC500_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_0 GIC500_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_0 GIC500_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_0 [0]: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-3-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721s2-main: Add CSI2 interrupts propertyYemike Abhilash Chandra
Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J721S2 TRM [0]. Interrupt Line | Source Interrupt --------------------|----------------------------- GIC500SS_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_OUT_0 GIC500SS_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_OUT_0 GIC500SS_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_OUT_0 GIC500SS_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_OUT_0 [0]: https://www.ti.com/lit/zip/spruj28 Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20250808095804.544298-2-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-am62a-phycore-som: Add 1.4GHz opp entryWadim Egorov
The phyCORE-AM62Ax is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20250805090021.1407753-2-w.egorov@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-am642-phyboard-electra: Add ti,pa-stats propertyWadim Egorov
Add ti,pa-stats phandles. This is a phandle to PA_STATS syscon regmap and will be used to dump IET related statistics for ICSSG Driver. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20250804105450.2322647-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-am68-sk: Enable DSI on DisplayPort-0Jayesh Choudhary
Enable DSI support for AM68-SK platform. Add DT node for DSI2eDP bridge. The DSI to eDP bridge is sn65dsi86 on the board. Add the endpoint nodes to describe connection from: DSS => DSI => SN65DSI86 bridge => DisplayPort-0 Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-8-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1Jayesh Choudhary
Enable DSI display for J721S2 EVM. Add the endpoint nodes to describe connection from: DSS => DSI Bridge => DSI to eDP bridge => DisplayPort-1 Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-7-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721s2-som-p0: Add DSI to eDPRahul T R
Add DT nodes for DSI to eDP bridge. The DSI to eDP bridge used is SN65DSI86 on SOM. Signed-off-by: Rahul T R <r-ravikumar@ti.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-6-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721s2-common-proc-board: Add main_i2c4 instanceJayesh Choudhary
Add dt node for main_i2c4 instance along with required pinmuxing. Also add the gpio expander 'exp4' required by display connector. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-5-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j721s2-main: Add DSI & DSI PHYRahul T R
Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Rahul T R <r-ravikumar@ti.com> [j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-4-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable DisplayPort-1Jayesh Choudhary
Enable DSI display for J784S4 EVM. Add DT node for DSI-to-eDP bridge. The DSI to eDP bridge is SN65DSI86 on the board. Add the endpoint nodes to describe connection from: DSS => DSI => SN65DSI86 bridge => DisplayPort-1 Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: ti: k3-j784s4-j742s2-main-common: Add DSI & DSI PHYJayesh Choudhary
Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250716060114.52122-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-08-13arm64: dts: exynos990-r8s: Enable USBIgor Belwon
Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-5-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990-c1s: Enable USBIgor Belwon
Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-4-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990-x1s-common: Enable USBIgor Belwon
The x1s family uses a shared USB configuration. Enable both the USB PHY as well as the DWC3 controller. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-3-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990: Add USB nodesIgor Belwon
Add USB controller and USB PHY controller nodes for use in the Exynos990 SoC. This SoC supports USB full-speed, high-speed and super-speed modes. Due to the inability to test PIPE3, USB super-speed is not enabled, and the USB PHY is only configured for UTMI+ operation for now. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-2-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990: Enable watchdog timerIgor Belwon
Enable the two watchdog timer clusters (cl0, cl2) present on the Exynos990 SoC. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-1-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos: Add Ethernet node for E850-96 boardSam Protsenko
The E850-96 board has a hard-wired LAN9514 chip which acts as a USB hub and Ethernet bridge. It's being discovered dynamically when the USB bus gets enumerated, but the corresponding Ethernet device tree node is still needed for the bootloader to pass the MAC address through. Add LAN9514 nodes as described in [1]. 'local-mac-address' property (in the 'ethernet' node) is used for MAC address handover from the bootloader to Linux. [1] Documentation/devicetree/bindings/net/microchip,lan95xx.yaml Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250731234532.12903-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13block: switch ->getgeo() to struct gendiskAl Viro
Instances are happier that way and it makes more sense anyway - the only part of the result that is related to partition we are given is the start sector, and that has been filled in by the caller. Everything else is a function of the disk. Only one instance (DASD) is ever looking at anything other than bdev->bd_disk and that one is trivial to adjust. Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Jens Axboe <axboe@kernel.dk> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2025-08-12arm64: dts: qcom: ipq5424: Enable cpufreqSricharan Ramabadhran
Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for CPU clock scaling. Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related entries, fix dt-bindings errors ] Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: x1e80100: Add videoccStephan Gerhold
Add the video clock controller for X1E80100, similar to sm8550.dtsi. It provides the needed clocks/power domains for the iris video codec. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-6-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: defconfig: Enable QCS615 clock controllersTaniya Das
Enable the QCS615 display, video, camera and graphics clock controller for their respective functionalities on the Qualcomm QCS615 ride platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-10-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EPMrinmay Sarkar
The maximum link speed was previously restricted to Gen3 due to the absence of Gen4 equalization support in the driver. As Gen4 equalization is already supported by the PCIe controller driver, remove the max-link-speed property. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-2-2df83ed6a373@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22Eric Gonçalves
Adds new device support for the Samsung Galaxy S22 (SM-S901E) phone Working features: - simple-framebuffer - side buttons - storage - usb Signed-off-by: Eric Gonçalves <ghatto404@gmail.com> Link: https://lore.kernel.org/r/20250615204438.1130213-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: sdm632-fairphone-fp3: Enable display and GPULuca Weiss
Add the description for the display panel found on this phone. Unfortunately the LCDB module on PMI632 isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Link: https://lore.kernel.org/r/20250611-fp3-display-v4-4-ef67701e7687@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: ipq5424: Describe the 4-wire UART SEKathiravan Thirumoorthy
QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the first SE, which supports a 4-wire UART configuration suitable for applications such as HS-UART. Note that the required initialization for this SE is not handled by the bootloader. Therefore, add the SE node in the device tree but keep it reserved. Enable it once Linux gains support for configuring the SE, allowing to use in relevant RDPs. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12Merge tag 'snp_cache_coherency' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip - Add a mitigation for a cache coherency vulnerability when running an SNP guest which makes sure all cache lines belonging to a 4K page are evicted after latter has been converted to a guest-private page [ SNP: Secure Nested Paging - not to be confused with Single Nucleotide Polymorphism, which is the more common use of that TLA. I am on a mission to write out the more obscure TLAs in order to keep track of them. Because while math tells us that there are only about 17k different combinations of three-letter acronyms using English letters (26^3), I am convinced that somehow Intel, AMD and ARM have together figured out new mathematics, and have at least a million different TLAs that they use. - Linus ] * tag 'snp_cache_coherency' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/sev: Evict cache lines during SNP memory validation
2025-08-12arm64: dts: qcom: sc7280: Add support for two additional DDR frequenciesPushpendra Singh
The SC7280 SoC now supports two additional frequencies. This patch add those frequencies to the BWMON OPP table and updates the frequency mapping table accordingly. These changes do not impact existing platforms, as the updated mapping only affects the highest OPP. On any given platform, this will continue to vote for the maximum available OPP. Signed-off-by: Pushpendra Singh <quic_pussin@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250702000120.2902158-1-quic_pussin@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdssBjorn Andersson
Like on other platforms, if the OS does not support recovering the state left by the bootloader it needs access to MDSS_CORE, so that it can clear the MDSS configuration. Until now it seems no version of the bootloaders have done so, but e.g. the Particle Tachyon ships with a bootloader that does leave the display in a state that results in a series of iommu faults. So let's provide the reset, to allow the OS to clear that state. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-3-83ceff1d48de@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHYBjorn Andersson
Only one PCIe controller has been described so far, but the SC7280 has two controllers/phys. Describe the second one as well. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250811-sc7280-pcie0-v1-1-6093e5b208f9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-12riscv: dts: thead: Add APB clocks for TH1520 GMACsYao Zi
Describe perisys-apb4-hclk as the APB clock for TH1520 SoC, which is essential for accessing GMAC glue registers. Fixes: 7e756671a664 ("riscv: dts: thead: Add TH1520 ethernet nodes") Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Drew Fustini <fustini@kernel.org> Tested-by: Drew Fustini <fustini@kernel.org> Link: https://patch.msgid.link/20250808093655.48074-5-ziyao@disroot.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-08-12x86/sev: Improve handling of writes to intercepted TSC MSRsNikunj A Dadhania
Currently, when a Secure TSC enabled SNP guest attempts to write to the intercepted GUEST_TSC_FREQ MSR (a read-only MSR), the guest kernel response incorrectly implies a VMM configuration error, when in fact it is the usual VMM configuration to intercept writes to read-only MSRs, unless explicitly documented. Modify the intercepted TSC MSR #VC handling: * Write to GUEST_TSC_FREQ will generate a #GP instead of terminating the guest * Write to MSR_IA32_TSC will generate a #GP instead of silently ignoring it However, continue to terminate the guest when reading from intercepted GUEST_TSC_FREQ MSR with Secure TSC enabled, as intercepted reads indicate an improper VMM configuration for Secure TSC enabled SNP guests. [ bp: simplify comment. ] Fixes: 38cc6495cdec ("x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests") Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/20250722074853.22253-1-nikunj@amd.com
2025-08-12ARM: dts: renesas: r7s72100: Add boot phase tagsMarek Vasut
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/A1 SoCs. All SoCs require BSC bus, PFC pin control, and OSTM0 timer access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains the PFC and OSTM IPs. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806150448.9669-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR supportMarek Vasut
Retronix R-Car V4H Sparrow Hawk EVTA1 is populated with Spansion S25FS512S, EVTB1 is populated with Winbond W77Q51NW. Describe the SPI NOR using the generic "jedec,spi-nor" compatible, because both FLASHes can be auto-detected based on their built-in IDs. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250806150048.9364-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0Biju Das
On RZ/G2LC SMARC EVK, CAN-FD channel0 is not populated, and currently we are deleting a wrong and nonexistent node. Fixing the wrong node would invoke a dtb warning message, as channel0 is a required property. Disable CAN-FD channel0 instead of deleting the node. Fixes: 46da632734a5 ("arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250801121959.267424-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: r9a09g047: Add DMAC nodesTommaso Merciai
Add nodes for the DMAC IPs found on the Renesas RZ/G3E SoC. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250801084825.471011-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced articleGeert Uytterhoeven
Move the article "the" before the full name of the board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/280176885acf46d117a0ab9a02c314e2b5cf250f.1753950938.git.geert+renesas@glider.be
2025-08-12arm64: dts: renesas: r9a09g087: Add SDHI nodesLad Prabhakar
Add the SDHI0-SDHI1 nodes to the RZ/N2H ("R9A09G087") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250707153533.287832-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: r9a09g077: Add SDHI nodesLad Prabhakar
Add the SDHI0-SDHI1 nodes to the RZ/T2H ("R9A09G077") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250707153533.287832-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: r9a09g087: Add I2C controller nodesLad Prabhakar
The Renesas RZ/N2H ("R9A09G087") SoC includes three I2C (RIIC) channels. Add device tree nodes for all three I2C controllers to the RZ/N2H SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250707153533.287832-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12arm64: dts: renesas: r9a09g077: Add I2C controller nodesLad Prabhakar
The Renesas RZ/T2H ("R9A09G077") SoC includes three I2C (RIIC) channels. Add device tree nodes for all three I2C controllers to the RZ/T2H SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250707153533.287832-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: qcom: sm6350: Add rpmh-stats nodeLuca Weiss
The qcom_stats driver allows querying sleep stats from various remoteprocs. Add a node to enable it. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250801-sm6350-rpmh-stats-v1-1-f1fb649d1095@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcm6490-fairphone-fp5: Enable USB audio offload supportLuca Weiss
Enable USB audio offloading which allows to play audio via a USB-C headset with lower power consumption and enabling some other features. This can be used like the following: $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On $ aplay --device=plughw:0,0 test.wav Compared to regular playback to the USB sound card no xhci-hcd interrupts appear during playback, instead the ADSP will be handling the USB transfers. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250801-fp5-usb-audio-offload-v1-2-240fc213d3d3@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc7280: Add q6usbdai nodeLuca Weiss
Add a node for q6usb which handles USB audio offloading, allowing to play audio via a USB-C headset with lower power consumption and enabling some other features. We also need to set num-hc-interrupters for the dwc3 for the q6usb to be able to use its sideband interrupter. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250801-fp5-usb-audio-offload-v1-1-240fc213d3d3@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc7180-acer-aspire1: drop deprecated DP suppliesDmitry Baryshkov
DP supplies were migrated to the corresponding DP PHY. Drop them from the DP controller node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-5-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: move data-lanes to the DP-out endpointDmitry Baryshkov
Support for the data-lanes declaration in the DP node is deprecated. Move them to the corresponding endpoint as recommended by the current DP bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-4-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-05 12:09:01 +0000