summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2025-09-11arm64: dts: add description for solidrun imx8mp som and cubox-mJosua Mayer
Add description for the SolidRun i.MX8M Plus based System on Module, and the CuBox-M. The SoM features: - 2x 1Gbps Ethernet with PHY - eMMC - 1/2/3/8GB DDR - MIPI-CSI Camera Connector (not described without specific camera) The CuBox-M is a complete product with enclosure featuring: - 1x 1Gbps RJ45 Ethernet Port - 2x USB-3.0 Type A - HDMI connector - microSD connector - microUSB connector for console (using fdtdi chip) - IR receiver - RTC with backup battery Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8: Use GIC_SPI for interrupt-map for readabilityKrzysztof Kozlowski
Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8qxp: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8-ss-hsio.dtsi:71.3-74.28: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8qm: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8qm-ss-hsio.dtsi:83.3-86.28: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mq: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mq.dtsi:1746.4-1749.43: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mp: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mp.dtsi:2184.4-2187.29: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mm: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mm.dtsi:1355.4-1358.29: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8dxl: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8dxl-ss-hsio.dtsi:45.3-48.27: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: fsl-ls1046a: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1046a.dtsi:334.5-346.26: Warning (interrupt_map): /soc/scfg@1570000/interrupt-controller@1ac:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: fsl-ls1043a: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1043a.dtsi:330.5-342.26: Warning (interrupt_map): /soc/scfg@1570000/interrupt-controller@1ac:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: fsl-ls1012a: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1012a.dtsi:548.4-551.32: Warning (interrupt_map): /soc/pcie@3400000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: freescale: imx8mp-moduline-display-106: Use phys to replace ↵Maud Spierings
xceiver-supply Fix the can tranceivers to actually use the new phy description instead of the regulator tweak. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mp: Add TechNexion EDM-G-IMX8M-PLUS SOM on WB-EDM-G carrier ↵Richard Hu
board Add support for TechNexion EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board. Key interfaces include: - Gigabit Ethernet - USB 3.0 - I2S, UART, SPI, I2C, PWM, GPIO Signed-off-by: Richard Hu <richard.hu@technexion.com> Signed-off-by: Ray Chang <ray.chang@technexion.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mp: add interconnect for lcdif-hdmiMarco Felsch
Add the missing interconnect for the lcdif-hdmi. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx95: Add msi-map for pci-ep deviceFrank Li
Add msi-map for pci-ep device. Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: dts: imx8mp: Add pclk clock and second power domain for the ISPLaurent Pinchart
The ISP HDR stitching registers are clocked by the pixel clock, which is gated by the MIPI_CSI2 power domain. Attempting to access those registers with the clock off locks up the system. Fix this by adding the pclk clock and the MIPI_CSI2 secondary power domain. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: imx: Kconfig: Adjust select after renamed config optionLukas Bulwahn
Commit 3f490a74a8a1 ("clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT") renames the config VF_PIT_TIMER to NXP_PIT_TIMER, but it misses adjusting a reference to VF_PIT_TIMER in arch/arm/mach-imx/Kconfig. Adjust the config reference to the new name. Fixes: 3f490a74a8a1 ("clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT") Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: imx6ul-tx6ul: Switch away from deprecated `phy-reset-gpios`Bence Csókás
The Ethernet PHY's reset GPIO should be specified in the node of the PHY itself, instead of the MAC (`fec`). The latter is deprecated, and was an i.MX-specific extension, incompatible with the new reset controller subsystem. Co-developed-by: Csaba Buday <buday.csaba@prolan.hu> Signed-off-by: Csaba Buday <buday.csaba@prolan.hu> Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: mba6ul: Add MicIn routingAlexander Stein
MicIn is connected to IN3_L. Add routing including the Mic Bias. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11arm64: defconfig: Enable Marvell WiFi-Ex USB driverAlexander Stein
MBa91xxCA (imx93-tqma9352-mba91xxca.dts) features a soldered, non-pluggable USB attached WiFi module. lsusb says: ID 1286:204e Marvell Semiconductor, Inc. Bluetooth and Wireless LAN Composite Device Enable the corresponding driver. To: Shawn Guo <shawnguo@kernel.org> To: Fabio Estevam <festevam@gmail.com> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: imx@lists.linux.dev Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: ls1021a-tsn: Remove redundant #address-cells for ethernet-switch@1Frank Li
Remove redundant #address-cells and #size-cells for ethernet-switch@1 because children node have not address. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dtb: ethernet-switch@1 (nxp,sja1105t): Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) from schema $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: ls1021a: Rename esdhc@1560000 to mmc@1560000Frank Li
Rename node name esdhc@1560000 to mmc@1560000 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtb: esdhc@1560000 (fsl,ls1021a-esdhc): $nodename:0: 'esdhc@1560000' does not match '^mmc(@.*)?$' from schema $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: ls1021a: Rename 'mdio-mux-emi1' to 'mdio-mux@54'Frank Li
Rename 'mdio-mux-emi1' to 'mdio-mux@54'. Add fallback compatible string mdio-mux. Fix below warning: arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed: 'bank-width', 'device-width', 'mdio-mux-emi1' do not match any of the regexes: '^mdio-mux@[a-f0-9,]+$', 'pinctrl-[0-9]+' Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: ls1021a: Rename node name nor to flashFrank Li
Rename node name nor to flash to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-twr.dtb: memory-controller@1530000 (fsl,ifc): 'nor@0,0' does not match any of the regexes: '(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$', '^nand@[a-f0-9]+(,[a-f0-9]+)+$', '^pinctrl-[0-9]+$' Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-09-11ARM: dts: lpc32xx: Correct PL080 DMA controller device node nameVladimir Zapolskiy
Rename PL080 DMA controller device node name to the expected one. The issue was reported by a dt binding checker: dma@31000000: $nodename:0: 'dma@31000000' does not match '^dma-controller(@.*)?$' Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controllerVladimir Zapolskiy
For DMA controllers it is required to specify a number of the cells for users. The change eliminates the next build time reported warning: dma@31000000: '#dma-cells' is a required property Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IPVladimir Zapolskiy
The SD/MMC controller on NXP LPC32xx SoC is ARM PrimeCell PL180, it is reported by the driver: mmci-pl18x 20098000.sd: mmc0: PL180 manf 41 rev0 at 0x20098000 irq 36,37 (pio) Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc32xx: Correct SD/MMC controller device node nameVladimir Zapolskiy
Change the PL180 SD/MMC controller device node name to the expected 'mmc' one. The change removes a reported warning: sd@20098000: $nodename:0: 'sd@20098000' does not match '^mmc(@.*)?$' Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc32xx: Correct motor PWM device tree node nameVladimir Zapolskiy
Change once a customly selected 'mpwm' node name in favour of the expected 'pwm' one. The change eliminates a reported warning: mpwm@400e8000: $nodename:0: 'mpwm@400e8000' does not match '^pwm(@.*|-([0-9]|[1-9][0-9]+))?$' Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cellsVladimir Zapolskiy
Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format") both types of PWM controlles on NXP LPC32xx SoC fairly gained 3 cells, reflect it in the platform dtsi file. The change removes a dt binding checker warning: mpwm@400e8000: #pwm-cells:0:0: 3 was expected Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc18xx: add missed arm,num-irq-priority-bitsFrank Li
Add missed arm,num-irq-priority-bits to fix below CHECK_DTBS warning: arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controllerFrank Li
Add #address-cells and #szie-cells for spi flash controller to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #address-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #size-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdioFrank Li
Change node name mdio0 to mdio to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: ethernet@40010000 (nxp,lpc1850-dwmac): Unevaluated properties are not allowed ('mdio0' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'Frank Li
Change node name 'button[0-9]' to button-[0-9]' to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: pca_buttons (gpio-keys-polled): 'button0', ... do not match any of the regexes: '^(button|...', 'pinctrl-[0-9]+' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92Frank Li
Add power-supply for innolux,at070tn92 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: panel (innolux,at070tn92): 'power-supply' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc: add cfg surfix in pinctrl child nodeFrank Li
Add cfg surfix in pinctrl child node to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: pinctrl@40086000 (nxp,lpc1850-scu): ssp-pins: 'ssp1_cs', 'ssp1_miso_mosi', 'ssp1_sck' do not match any of the regexes: '^pinctrl-[0-9]+$', '_cfg$' from schema $id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc: add #address-cells and #size-cells for sram nodeFrank Li
Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: sram@2,0 (mmio-sram): '#address-cells' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc18xx: swap clock-names bic and cuiFrank Li
Swap clock-names bic and cui to fix below CHECK_DTB warnings: /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:0: 'biu' was expected from schema $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:1: 'ciu' was expected Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0Frank Li
Change node name 'flash' to 'flash@0' to fix below CHECK_DTB warnings. arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): Unevaluated properties are not allowed ('flash' was unexpected) from schema $id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc18xx: rename node name mmcsd to mmcFrank Li
Change node name mmcsd to mmc to fix CHECK_DTB warnings: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: mmcsd@40004000 (snps,dw-mshc): $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-11ARM: dts: lpc18xx: rename node name flash-controller to spiFrank Li
Anyway it is SPI controller although intent to connect qspi flash. Rename node name flash-controller to spi to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): $nodename:0: 'flash-controller@40003000' does not match '^spi(@.*|-([0-9]|[1-9][0-9]+))?$ Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2025-09-10KVM: TDX: Do not retry locally when the retry is caused by invalid memslotSean Christopherson
Avoid local retries within the TDX EPT violation handler if a retry is triggered by faulting in an invalid memslot, indicating that the memslot is undergoing a removal process. Faulting in a GPA from an invalid memslot will never succeed, and holding SRCU prevents memslot deletion from succeeding, i.e. retrying when the memslot is being actively deleted will lead to (breakable) deadlock. Opportunistically export kvm_vcpu_gfn_to_memslot() to allow for a per-vCPU lookup (which, strictly speaking, is unnecessary since TDX doesn't support SMM, but aligns the TDX code with the MMU code). Fixes: b0327bb2e7e0 ("KVM: TDX: Retry locally in TDX EPT violation handler on RET_PF_RETRY") Reported-by: Reinette Chatre <reinette.chatre@intel.com> Closes: https://lore.kernel.org/all/20250519023737.30360-1-yan.y.zhao@intel.com [Yan: Wrote patch log, comment, fixed a minor error, function export] Signed-off-by: Yan Zhao <yan.y.zhao@intel.com> Link: https://lore.kernel.org/r/20250822070523.26495-1-yan.y.zhao@intel.com [sean: massage changelog, relocate and tweak comment] Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10KVM: x86/mmu: Return -EAGAIN if userspace deletes/moves memslot during prefaultSean Christopherson
Return -EAGAIN if userspace attempts to delete or move a memslot while also prefaulting memory for that same memslot, i.e. force userspace to retry instead of trying to handle the scenario entirely within KVM. Unlike KVM_RUN, which needs to handle the scenario entirely within KVM because userspace has come to depend on such behavior, KVM_PRE_FAULT_MEMORY can return -EAGAIN without breaking userspace as this scenario can't have ever worked (and there's no sane use case for prefaulting to a memslot that's being deleted/moved). And also unlike KVM_RUN, the prefault path doesn't naturally guarantee forward progress. E.g. to handle such a scenario, KVM would need to drop and reacquire SRCU to break the deadlock between the memslot update (synchronizes SRCU) and the prefault (waits for the memslot update to complete). However, dropping SRCU creates more problems, as completing the memslot update will bump the memslot generation, which in turn will invalidate the MMU root. To handle that, prefaulting would need to handle pending KVM_REQ_MMU_FREE_OBSOLETE_ROOTS requests and do kvm_mmu_reload() prior to mapping each individual. I.e. to fully handle this scenario, prefaulting would eventually need to look a lot like vcpu_enter_guest(). Given that there's no reasonable use case and practically zero risk of breaking userspace, punt the problem to userspace and avoid adding unnecessary complexity to the prefault path. Note, TDX's guest_memfd post-populate path is unaffected as slots_lock is held for the entire duration of populate(), i.e. any memslot modifications will be fully serialized against TDX's flavor of prefaulting. Reported-by: Reinette Chatre <reinette.chatre@intel.com> Closes: https://lore.kernel.org/all/20250519023737.30360-1-yan.y.zhao@intel.com Debugged-by: Yan Zhao <yan.y.zhao@intel.com> Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Link: https://lore.kernel.org/r/20250822070347.26451-1-yan.y.zhao@intel.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10KVM: x86: Move vector_hashing into lapic.cSean Christopherson
Move the vector_hashing module param into lapic.c now that all usage is contained within the local APIC emulation code. Opportunistically drop the accessor and append "_enabled" to the variable to help capture that it's a boolean module param. No functional change intended. Link: https://lore.kernel.org/r/20250821214209.3463350-4-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10KVM: x86: Make "lowest priority" helpers local to lapic.cSean Christopherson
Make various helpers for resolving lowest priority IRQs local to lapic.c now that kvm_irq_delivery_to_apic() lives in lapic.c as well. No functional change intended. Link: https://lore.kernel.org/r/20250821214209.3463350-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10KVM: x86: Move kvm_irq_delivery_to_apic() from irq.c to lapic.cSean Christopherson
Move kvm_irq_delivery_to_apic() to lapic.c as it is specific to local APIC emulation. This will allow burying more local APIC code in lapic.c, e.g. the various "lowest priority" helpers. No functional change intended. Link: https://lore.kernel.org/r/20250821214209.3463350-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10KVM: SVM: Sync TPR from LAPIC into VMCB::V_TPR even if AVIC is activeMaciej S. Szmigiero
Commit 3bbf3565f48c ("svm: Do not intercept CR8 when enable AVIC") inhibited pre-VMRUN sync of TPR from LAPIC into VMCB::V_TPR in sync_lapic_to_cr8() when AVIC is active. AVIC does automatically sync between these two fields, however it does so only on explicit guest writes to one of these fields, not on a bare VMRUN. This meant that when AVIC is enabled host changes to TPR in the LAPIC state might not get automatically copied into the V_TPR field of VMCB. This is especially true when it is the userspace setting LAPIC state via KVM_SET_LAPIC ioctl() since userspace does not have access to the guest VMCB. Practice shows that it is the V_TPR that is actually used by the AVIC to decide whether to issue pending interrupts to the CPU (not TPR in TASKPRI), so any leftover value in V_TPR will cause serious interrupt delivery issues in the guest when AVIC is enabled. Fix this issue by doing pre-VMRUN TPR sync from LAPIC into VMCB::V_TPR even when AVIC is enabled. Fixes: 3bbf3565f48c ("svm: Do not intercept CR8 when enable AVIC") Cc: stable@vger.kernel.org Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Reviewed-by: Naveen N Rao (AMD) <naveen@kernel.org> Link: https://lore.kernel.org/r/c231be64280b1461e854e1ce3595d70cde3a2e9d.1756139678.git.maciej.szmigiero@oracle.com [sean: tag for stable@] Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-09-10Revert "KVM: arm64: Split kvm_pgtable_stage2_destroy()"Oliver Upton
This reverts commit 0e89ca13ee5ff41b437bb2a003c0eaf34ea43555. The functional change that depended on this refactoring has been found to be quite problematic. Reverting the whole pile to start fresh when new fixes are available. Message-ID: <20250910180930.3679473-3-oliver.upton@linux.dev> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-09-10Revert "KVM: arm64: Reschedule as needed when destroying the stage-2 ↵Oliver Upton
page-tables" This reverts commit e9abe311f35631a999fe38c86f26f0e48ffe46d5. syzkaller has managed to tease out multiple bugs in this change and fixing-forward didn't remedy the situation. Considering newly-introduced memory safety issues the potential for scheduler stalls don't seem that bad in comparison Link: https://lore.kernel.org/kvmarm/68c09802.050a0220.3c6139.000d.GAE@google.com/ Message-ID: <20250910180930.3679473-2-oliver.upton@linux.dev> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2025-09-10arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset settingChen-Yu Tsai
The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 board") Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250908181059.1785605-9-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-07 05:31:24 +0000