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2025-10-27Merge 6.18-rc3 into driver-core-nextGreg Kroah-Hartman
We need the driver core fixes in here as well to build on top of. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-27ARM: dts: imx7ulp: remove bias-pull-upFrank Li
i.MX7ULP pinctrl don't support bias-pull-up property. So remove it to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dtb: pinctrl@40ac0000 (fsl,imx7ulp-iomuxc1): lpuart4grp: 'bias-pull-up' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: remove undocumented clock-names for ov5642Frank Li
Remove undocumented clock-names for ov5642 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dtb: camera@3c (ovti,ov5642): 'clock-names' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5642.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: add device_type for memory nodeFrank Li
Add device_type for memory node to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dtb: / (ge,imx6dl-b105pv2): memory@10000000: 'device_type' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: Add bus type for parallel ov5640Frank Li
Add bus type for parallel ov5640 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: camera@42 (ovti,ov5642): port:endpoint:hsync-active: False schema does not allow 1 Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6q-cm-fx6.dts: add supplies for wm8731Frank Li
Add supplies for wm8731 to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dtb: codec@1a (wlf,wm8731): 'AVDD-supply' is a required property from schema $id: http://devicetree.org/schemas/sound/wlf,wm8731.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6qdl-skov-cpu fix typo interruptFrank Li
Fix typo interrupt, which should be 'interrupts'. Fix below CHECK_DTBS warnings. arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dtb: switch@0 (microchip,ksz8873): Unevaluated properties are not allowed ('interrupt', 'pinctrl-names' were unexpected) from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx: remove redundant linux,phandleFrank Li
Remove redundant linux,phandle to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dtb: pmic@3c (lltc,ltc3676): regulators:sw3: Unevaluated properties are not allowed ('linux,phandle' was unexpected) Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6ull-dhcom-pdk2: rename power-supply to vcc-supply for touchscreenFrank Li
Rename power-supply to vcc-supply for touchscreen to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dtb: touchscreen@38 (edt,edt-ft5406): Unevaluated properties are not allowed ('power-supply' was unexpected) Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx: add power-supply for lcd panelFrank Li
Add power-supply for lcd panel to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-evi.dtb: panel (sharp,lq101k1ly04): 'power-supply' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mp pollux: add displays for expansion boardYannic Moog
The same displays that can be connected directly to the imx8mp-phyboard-pollux can also be connected to the expansion board PEB-AV-10. For displays connected to the expansion board, a second LVDS channel of the i.MX 8M Plus SoC is used and only a single display connected to the SoC LVDS display bridge at a given time is supported. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mp pollux: add expansion board overlayYannic Moog
An expansion board (PEB-AV-10) may be connected to the imx8mp-phyboard-pollux. Its main purpose is to provide multimedia interfaces, featuring a 3.5mm headphone jack, a USB-A port and LVDS as well as backlight connectors. Introduce the expansion board as dtsi, as it may be used standalone as an expansion board, as well as in combination with display panels. These display panels will include the dtsi. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mp pollux: add display overlaysYannic Moog
imx8mp-phyboard-pollux had a display baked into its board dts file. However this approach does not truly discribe the hardware and is not suitable when using different displays. Move display specific description into an overlay and add the successor display for the phyboard-pollux as an additional overlay. Reviewed-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: im8mp-phy{board,core}: update licenseYannic Moog
Change license from GPL-2.0 to GPL-2.0-or-later OR MIT. Use syntax as defined in the SPDX standard. Also remove individual authorship. Acked-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27Merge 6.18-rc3 into char-misc-nextGreg Kroah-Hartman
We need the fixes in here, and it resolves a merge conflict in: drivers/misc/amd-sbi/Kconfig Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-27arm64: dts: imx95: Fix MSI mapping for PCIe endpoint nodesFrank Li
The msi-map property was incorrectly applied to pcie0-ep instead of pcie1-ep. Correct the msi-map for both pcie0-ep and pcie1-ep nodes. Fixes: bbe4b2f7d6533 ("arm64: dts: imx95: Add msi-map for pci-ep device") Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6qdl-nitrogen6_max: rename i2c<n>mux to i2cFrank Li
Rename i2c<n>mux to i2c to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dtb: i2c2mux (i2c-mux-gpio): $nodename:0: 'i2c2mux' does not match '^(i2c-?)?mux' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6ull-phytec-tauri: remove extra space before jedec,spi-norFrank Li
Remove extra space in " jedec,spi-nor" to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dtb: /soc/bus@2000000/spba-bus@2000000/spi@2008000/flash@2: failed to match any schema with compatible: [' jedec,spi-nor'] Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6q-utilite-pro: add missing required property for pciFrank Li
Add device_type, bus-range, ranges for pci nodes. Rename intel,i211 to ethernet to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dtb: pcie@0,0: 'device_type' is a required property from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml# arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dtb: pcie@0,0: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/pci/pci-bus-common.yaml arm/boot/dts/nxp/imx/imx6q-utilite-pro.dtb: pcie@0,0: 'intel,i211@pcie0,0' does not match any of the regexes: '.*-names$', '.*-supply$', '^#.*-cells$', '^#[a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z0-9][a-zA-Z0-9#,+\\-._]{0,63}$', '^[a-zA-Z0-9][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+(,[0-9a-fA-F]+)*$', '^__.*__$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/dt-core.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6-tbs2910: rename ir_recv to ir-receiverFrank Li
Rename ir_recv to ir-receiver to fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx6q-tbs2910.dtb: ir_recv (gpio-ir-receiver): $nodename:0: 'ir_recv' does not match '^ir(-receiver)?(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/media/gpio-ir-receiver.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: remove pinctrl-name if pinctrl-0 doesn't existFrank Li
Remove redundant pinctrl-name since pinctrl-0 doesn't exist to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dtb: pinctrl@20e0000 (fsl,imx6q-iomuxc): 'pinctrl-0' is a dependency of 'pinctrl-names' from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: change voltage-divider's io-channel-cells to 1Frank Li
Change voltage-divider's io-channel-cells to 1 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dtb: voltage-divider-vaccu (voltage-divider): #io-channel-cells: 1 was expected from schema $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: remove gpio suffix for regulatorFrank Li
Remove gpio suffix for regulator to fix below CHECK_DTBS warnings: (fsl,imx6sx-sdb): regulator-pcie-gpio: {'compatible': ['regulator-fixed'], 'phandle': 69} is not of type 'array' from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6qdl-ts4900: rename ngpio to ngpiosFrank Li
Rename ngpio to ngpios to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dtb: gpio@28 (technologic,ts4900-gpio): 'ngpio' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/trivial-gpio.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: rename m95m02 to eepromFrank Li
rename m95m02 to eeprom to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-evi.dtb: m95m02@1 (st,m95m02): $nodename: 'anyOf' conditional failed, one must be fixed: 'm95m02@1' does not match '^eeprom@[0-9a-f]{1,2}$' 'm95m02@1' does not match '^fram@[0-9a-f]{1,2}$' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: rename touch-thermal0 to touch-0-thermalFrank Li
Rename touch-thermal0 to touch-0-thermal to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dtb: thermal-zones: 'touch-thermal0', 'touch-thermal1' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx6: rename stmpgpio to gpioFrank Li
Rename stmpgpio to gpio and add gpio-controller and interrupt-controller. Rename stmpe_adc to adc. Move interrupt-controller and gpio-controller under gpio node. to fix below CHECK_DTBS warnings: /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dtb: stmpe1601@40 (st,stmpe1601): gpio: 'interrupt-controller' is a required property from schema $id: http://devicetree.org/schemas/mfd/st,stmpe.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dtb: gpio (st,stmpe-gpio): 'interrupt-controller' is a required property from schema $id: http://devicetree.org/schemas/gpio/st,stmpe-gpio.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dtb: stmpe1601@44 (st,stmpe1601): gpio: 'interrupt-controller' is a required property from schema $id: http://devicetree.org/schemas/mfd/st,stmpe.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dtb: gpio (st,stmpe-gpio): 'interrupt-controller' is a required property from schema $id: http://devicetree.org/schemas/gpio/st,stmpe-gpio.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: ls1046a-qds: describe the two on-board SFP+ cagesIoana Ciornei
Describe the two SFP+ cages present on the LS1046AQDS board and their associated I2C buses and GPIO lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: lx2160a-rdb: fully describe the two SFP+ cagesIoana Ciornei
Describe the two SFP+ cages found on the LX2160ARDB board with their respective I2C buses and GPIO lines. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: ls1046a-qds: describe the FPGA based GPIO controllerIoana Ciornei
The QIXIS FPGA node is extended so that it describes the GPIO controller responsible for all the status presence lines on both SFP+ cages as well as the IO SLOTs present on the board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllersIoana Ciornei
Describe the FPGA present on the LX2160ARDB board as a simple-mfd I2C device. The FPGA presents registers that deal with power-on-reset timing, muxing, SFP cage monitoring and control etc. Also add the two GPIO controllers responsible for monitoring and controlling the SFP+ cages used for MAC5 and MAC6. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: add Protonic PRT8ML boardJonas Rebmann
Add devicetree for the Protonic PRT8ML. The board is similar to the Protonic PRT8MM but i.MX8MP based. Some features have been removed as the drivers haven't been mainlined yet or other issues where encountered: - Stepper motors to be controlled using motion control subsystem - MIPI/DSI to eDP USB alt-mode - Onboard T1 ethernet (10BASE-T1L+PoDL, 100BASE-T1+PoDL, 1000BASE-T1) Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8-ss-img: Avoid gpio0_mipi_csi GPIOs being deferredJoão Paulo Gonçalves
The gpio0_mipi_csi DT nodes are enabled by default, but they are dependent on the irqsteer_csi nodes, which are not enabled. This causes the gpio0_mipi_csi GPIOs to be probe deferred. Since these GPIOs can be used independently of the CSI controller, enable irqsteer_csi by default too to prevent them from being deferred and to ensure they work out of the box. Fixes: 2217f8243714 ("arm64: dts: imx8: add capture controller for i.MX8's img subsystem") Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mp: add cpuidle cooling device to the alert trip pointMartin Kepplinger-Novaković
Idle-inject up to 50% of all cpu's time in order to help cpufreq to keep the temperature below the trip points. Signed-off-by: Martin Kepplinger-Novaković <martink@posteo.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mp: add idle cooling devices to cpu coreMartin Kepplinger-Novaković
The thermal framework can use the cpu-idle-states as described for imx8mp as an alternative or in parallel to cpufreq. Add the DT node to the cpu so the cooling devices will be present and the thermal zone descriptions can use them. Signed-off-by: Martin Kepplinger-Novaković <martink@posteo.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm: imx_v6_v7_defconfig: enable ext4 directlyAndreas Kemnade
In former times, ext4 was enabled implicitely by enabling ext3 but with the ext3 fs gone, it does not get enabled, which lets devices fail to mount root on non-initrd based boots with an ext4 root. Fixes: d6ace46c82fd ("ext4: remove obsolete EXT3 config options") Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27ARM: dts: imx53: enable PMIC RTC on imx53-qsrbAlexander Kurz
The RTC inside mc34708 is supported by RTC_DRV_MC13XXX since v3.6-rc1. Enable the PMIC RTC on the imx53-qsrb. Without a battery the RTC may be powered via the micro-USB connector when main 5V power is not available. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: ti: k3-am62p: Fix memory ranges for GPURandolph Sapp
Update the memory region listed in the k3-am62p.dtsi for the BXS-4-64 GPU to match the Main Memory Map described in the TRM [1]. [1] https://www.ti.com/lit/ug/spruj83b/spruj83b.pdf Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Randolph Sapp <rs@ti.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://patch.msgid.link/20250919193341.707660-2-rs@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-10-26crypto: x86/aes-gcm - optimize long AAD processing with AVX512Eric Biggers
Improve the performance of aes_gcm_aad_update_vaes_avx512() on large AAD (additional authenticated data) lengths by 4-8 times by making it use up to 512-bit vectors and a 4-vector-wide loop. Previously, it used only 256-bit vectors and a 1-vector-wide loop. Originally, I assumed that the case of large AADLEN was unimportant. Later, when reviewing the users of BoringSSL's AES-GCM code, I found that some callers use BoringSSL's AES-GCM API to just compute GMAC, authenticating lots of data but not en/decrypting any. Thus, I included a similar optimization in the BoringSSL port of this code. I believe it's wise to include this optimization in the kernel port too for similar reasons, and to align it more closely with the BoringSSL port. Another reason this function originally used 256-bit vectors was so that separate *_avx10_256 and *_avx10_512 versions of it wouldn't be needed. However, that's no longer applicable. To avoid a slight performance regression in the common case of AADLEN <= 16, also add a fast path for that case which uses 128-bit vectors. In fact, this case actually gets slightly faster too, since it saves a couple instructions over the original 256-bit code. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-9-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - optimize AVX512 precomputation of H^2 from H^1Eric Biggers
Squaring in GF(2^128) requires fewer instructions than a generic multiplication in GF(2^128). Take advantage of this when computing H^2 from H^1 in aes_gcm_precompute_vaes_avx512(). Note that aes_gcm_precompute_vaes_avx2() already uses this optimization. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-8-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - revise some comments in AVX512 codeEric Biggers
- Fix some references to field names in struct aes_gcm_key_vaes_avx512. - Remove the mention of the counter having to start at 2. The assembly code doesn't actually assume that it does. Note that these changes improve consistency with aes-gcm-vaes-avx2.S. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-7-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - reorder AVX512 precompute and aad_update functionsEric Biggers
Now that the _aes_gcm_precompute macro is instantiated only once, replace it directly with a function definition. Also, move aes_gcm_aad_update_vaes_avx512() to a different location in the file so that it's consistent with aes-gcm-vaes-avx2.S and also the BoringSSL port of this code. No functional changes. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-6-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - clean up AVX512 code to assume 512-bit vectorsEric Biggers
aes-gcm-vaes-avx512.S (originally aes-gcm-avx10-x86_64.S) was designed to support multiple maximum vector lengths, while still utilizing AVX512 / AVX10 features such as the increased number of vector registers. However, the support for multiple maximum vector lengths turned out to not be useful. Support for maximum vector lengths other than 512 bits was removed from the AVX10 specification, which leaves "avoiding overly-eager downclocking" as the only remaining use case for limiting AVX512 / AVX10 code to 256-bit vectors. But this issue has gone away in new CPUs, and the separate VAES+AVX2 code which I ended up having to write anyway provides nearly as good 256-bit support. Therefore, clean up this code to not be written in terms of a generic vector length, but rather just assume 512-bit vectors. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-5-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - rename avx10 and avx10_512 to avx512Eric Biggers
With the "avx10_256" code removed and the AVX10 specification having been changed to basically just be a re-packaged AVX512, the "avx10_512" name no longer makes sense. Replace it with "avx512". While doing this, also add the "vaes_" prefix in places that didn't already have it. The result is that the two VAES optimized implementations are consistently called vaes_avx2 and vaes_avx512. (Also drop the "-x86_64" part of the assembly filename, to keep it from getting too long. There's no 32-bit version of this code, and the fact that it's 64-bit is unremarkable; it's the norm for new code.) Note: although aes_gcm_aad_update_vaes_avx512() (previously called aes_gcm_aad_update_vaes_avx10()) uses at most 256-bit vectors, it still depends on the AVX512 CPU feature. So its new name is still accurate. Also, a later commit will make it sometimes use 512-bit vectors anyway. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-4-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - remove VAES+AVX10/256 optimized codeEric Biggers
Remove the VAES+AVX10/256 optimized implementation of AES-GCM. It's no longer expected to be useful for future CPUs, since Intel changed the AVX10 specification to require 512-bit vectors. In addition, it's no longer very useful to serve as the 256-bit fallback for older Intel CPUs (Ice Lake and Tiger Lake) that downclock too eagerly when 512-bit vectors are used. This is because I ended up writing another 256-bit implementation anyway, using VAES+AVX2. The VAES+AVX2 implementation is almost as fast as the VAES+AVX10/256 one, as shown by the following tables. So, let's just use it instead. Table 1: AES-256-GCM encryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -2% | -1% | 0% | -2% | -2% | 3% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | 1% | 0% | 4% | 2% | -6% | Table 2: AES-256-GCM decryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -1% | -1% | 1% | -2% | 0% | 2% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -1% | 4% | 1% | 0% | -5% | Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-3-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-26crypto: x86/aes-gcm - add VAES+AVX2 optimized codeEric Biggers
Add an implementation of AES-GCM that uses 256-bit vectors and the following CPU features: Vector AES (VAES), Vector Carryless Multiplication (VPCLMULQDQ), and AVX2. It doesn't require AVX512. So unlike the existing VAES+AVX512 code, it works on CPUs that support VAES but not AVX512, specifically: - AMD Zen 3, both client and server - Intel Alder Lake, Raptor Lake, Meteor Lake, Arrow Lake, and Lunar Lake. (These are client CPUs.) - Intel Sierra Forest. (This is a server CPU.) On these CPUs, this VAES+AVX2 code is much faster than the existing AES-NI code. The AES-NI code uses only 128-bit vectors. These CPUs are widely deployed, making VAES+AVX2 code worthwhile even though hopefully future x86_64 CPUs will uniformly support AVX512. This implementation will also serve as the fallback 256-bit implementation for older Intel CPUs (Ice Lake and Tiger Lake) that support AVX512 but downclock too eagerly when 512-bit vectors are used. Currently, the VAES+AVX10/256 implementation serves that purpose. A later commit will remove that and just use the VAES+AVX2 one. (Note that AES-XTS and AES-CTR already successfully use this approach.) I originally wrote this AES-GCM implementation for BoringSSL. It's been in BoringSSL for a while now, including in Chromium. This is a port of it to the Linux kernel. The main changes in the Linux version include: - Port from "perlasm" to a standard .S file. - Align all assembly functions with what aesni-intel_glue.c expects, including adding support for lengths not a multiple of 16 bytes. - Rework the en/decryption of the final 1 to 127 bytes. This commit increases AES-256-GCM throughput on AMD Milan (Zen 3) by up to 74%, as shown by the following tables: Table 1: AES-256-GCM encryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ AMD Milan (Zen 3) | 67% | 59% | 61% | 39% | 23% | 27% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ AMD Milan (Zen 3) | 14% | 12% | 7% | 7% | 0% | Table 2: AES-256-GCM decryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ AMD Milan (Zen 3) | 74% | 65% | 65% | 44% | 23% | 26% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ AMD Milan (Zen 3) | 12% | 11% | 3% | 2% | -3% | Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-2-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2025-10-27ARM: dts: imx6q-evi: fix rtc compatibleAlexandre Belloni
The correct compatible is nxp,pcf2123 Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pinTeresa Remmet
Disable Hysteresis Enable Field in pad ctl register for USB OC pin as this is more appropriate for the signal form in our case. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: imx8mm-phyboard-polis-rdk: Add USB1 OC pin configurationTeresa Remmet
Add USB1 OC pin configuration for proper over-current detection. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-10-27arm64: dts: freescale: add initial support for i.MX 95 Verdin Evaluation Kit ↵Marek Vasut
(EVK) Add initial support for i.MX 95 Verdin Evaluation Kit (EVK), which used to be the Titan EVK. Currently supported is lpuart1 as console, SDHC1/2/3 as storage, WM8904 Audio, USB3.0 and ENETC ethernet RGMII Gigabit port. Note that the SoM used in this EVK is a derivative SoM from Verdin line of SoMs, an actual i.MX95 Verdin SoM is under development. [1] https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95-evaluation-kit Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Tested-by: João Paulo Gonçalves <joao.goncalves@toradex.com> # i.MX95 Verdin EVK Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-22 02:42:35 +0000