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2024-02-08Merge tag 'percpu-for-6.8-rc4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu Pull percpu fix from Dennis Zhou: - fix riscv wrong size passed to local_flush_tlb_range_asid() * tag 'percpu-for-6.8-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu: riscv: Fix wrong size passed to local_flush_tlb_range_asid()
2024-02-07arch/arm/mm: fix major fault accounting when retrying under per-VMA lockSuren Baghdasaryan
The change [1] missed ARM architecture when fixing major fault accounting for page fault retry under per-VMA lock. The user-visible effects is that it restores correct major fault accounting that was broken after [2] was merged in 6.7 kernel. The more detailed description is in [3] and this patch simply adds the same fix to ARM architecture which I missed in [3]. Add missing code to fix ARM architecture fault accounting. [1] 46e714c729c8 ("arch/mm/fault: fix major fault accounting when retrying under per-VMA lock") [2] https://lore.kernel.org/all/20231006195318.4087158-6-willy@infradead.org/ [3] https://lore.kernel.org/all/20231226214610.109282-1-surenb@google.com/ Link: https://lkml.kernel.org/r/20240123064305.2829244-1-surenb@google.com Fixes: 12214eba1992 ("mm: handle read faults under the VMA lock") Reported-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Suren Baghdasaryan <surenb@google.com> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Gerald Schaefer <gerald.schaefer@linux.ibm.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2024-02-07KVM: x86: rename push to emulate_push for consistencyJulian Stecklina
push and emulate_pop are counterparts. Rename push to emulate_push and harmonize its function signature with emulate_pop. This should remove a bit of cognitive load when reading this code. Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de> Link: https://lore.kernel.org/r/20231009092054.556935-2-julian.stecklina@cyberus-technology.de Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-02-07KVM: x86: Clean up partially uninitialized integer in emulate_pop()Julian Stecklina
Explicitly zero out variables passed to emulate_pop() as output params to harden against consuming uninitialized data, and to make sanitizers happy. Many flows that use emulate_pop() pass an "unsigned long" so as to be able to hold the largest possible operand, but the actual number of bytes written is usually the word with of the vCPU. E.g. if the vCPU is in 16-bit or 32-bit mode (on a 64-bit host), the upper portion of the output param will be uninitialized. Passing around the uninitialized data is benign, as actual KVM usage of the output is also tied to the word width, but passing around uninitialized data makes some sanitizers rightly complain. Note, initializing the data in emulate_pop() is not a safe alternative, e.g. it would result in em_leave() clobbering RBP[31:16] if LEAVE were emulated with a 16-bit stack. Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de> Link: https://lore.kernel.org/r/20231009092054.556935-1-julian.stecklina@cyberus-technology.de [sean: massage changelog, drop em_popa() variable size change]] Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-02-07KVM: x86/emulator: emulate movbe with operand-size prefixThomas Prescher
The MOVBE instruction can come with an operand-size prefix (66h). In this, case the x86 emulation code returns EMULATION_FAILED. It turns out that em_movbe can already handle this case and all that is missing is an entry in respective opcode tables to populate gprefix->pfx_66. Signed-off-by: Thomas Prescher <thomas.prescher@cyberus-technology.de> Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20231212095938.26731-1-julian.stecklina@cyberus-technology.de Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-02-07riscv: Fix arch_tlbbatch_flush() by clearing the batch cpumaskAlexandre Ghiti
We must clear the cpumask once we have flushed the batch, otherwise cpus get accumulated and we end sending IPIs to more cpus than needed. Fixes: 54d7431af73e ("riscv: Add support for BATCHED_UNMAP_TLB_FLUSH") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Link: https://lore.kernel.org/r/20240130115508.105386-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-07Merge tag 'loongarch-fixes-6.8-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch fixes from Huacai Chen: "Fix acpi_core_pic[] array overflow, fix earlycon parameter if KASAN enabled, disable UBSAN instrumentation for vDSO build, and two Kconfig cleanups" * tag 'loongarch-fixes-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: LoongArch: vDSO: Disable UBSAN instrumentation LoongArch: Fix earlycon parameter if KASAN enabled LoongArch: Change acpi_core_pic[NR_CPUS] to acpi_core_pic[MAX_CORE_PIC] LoongArch: Select HAVE_ARCH_SECCOMP to use the common SECCOMP menu LoongArch: Select ARCH_ENABLE_THP_MIGRATION instead of redefining it
2024-02-07riscv: declare overflow_stack as exported from traps.cBen Dooks
The percpu area overflow_stacks is exported from arch/riscv/kernel/traps.c for use in the entry code, but is not declared anywhere. Add the relevant declaration to arch/riscv/include/asm/stacktrace.h to silence the following sparse warning: arch/riscv/kernel/traps.c:395:1: warning: symbol '__pcpu_scope_overflow_stack' was not declared. Should it be static? We don't add the stackinfo_get_overflow() call as for some of the other architectures as this doesn't seem to be used yet, so just silence the warning. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: be97d0db5f44 ("riscv: VMAP_STACK overflow detection thread-safe") Link: https://lore.kernel.org/r/20231123134214.81481-1-ben.dooks@codethink.co.uk Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-07riscv: Fix arch_hugetlb_migration_supported() for NAPOTAlexandre Ghiti
arch_hugetlb_migration_supported() must be reimplemented to add support for NAPOT hugepages, which is done here. Fixes: 82a1a1f3bfb6 ("riscv: mm: support Svnapot in hugetlb page") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240130120114.106003-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-07Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "x86 guest: - Avoid false positive for check that only matters on AMD processors x86: - Give a hint when Win2016 might fail to boot due to XSAVES && !XSAVEC configuration - Do not allow creating an in-kernel PIT unless an IOAPIC already exists RISC-V: - Allow ISA extensions that were enabled for bare metal in 6.8 (Zbc, scalar and vector crypto, Zfh[min], Zihintntl, Zvfh[min], Zfa) S390: - fix CC for successful PQAP instruction - fix a race when creating a shadow page" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: x86/coco: Define cc_vendor without CONFIG_ARCH_HAS_CC_PLATFORM x86/kvm: Fix SEV check in sev_map_percpu_data() KVM: x86: Give a hint when Win2016 might fail to boot due to XSAVES erratum KVM: x86: Check irqchip mode before create PIT KVM: riscv: selftests: Add Zfa extension to get-reg-list test RISC-V: KVM: Allow Zfa extension for Guest/VM KVM: riscv: selftests: Add Zvfh[min] extensions to get-reg-list test RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM KVM: riscv: selftests: Add Zihintntl extension to get-reg-list test RISC-V: KVM: Allow Zihintntl extension for Guest/VM KVM: riscv: selftests: Add Zfh[min] extensions to get-reg-list test RISC-V: KVM: Allow Zfh[min] extensions for Guest/VM KVM: riscv: selftests: Add vector crypto extensions to get-reg-list test RISC-V: KVM: Allow vector crypto extensions for Guest/VM KVM: riscv: selftests: Add scaler crypto extensions to get-reg-list test RISC-V: KVM: Allow scalar crypto extensions for Guest/VM KVM: riscv: selftests: Add Zbc extension to get-reg-list test RISC-V: KVM: Allow Zbc extension for Guest/VM KVM: s390: fix cc for successful PQAP KVM: s390: vsie: fix race during shadow creation
2024-02-07kvmclock: Unexport kvmclock clocksourcePeter Hilber
The KVM PTP driver now refers to the clocksource ID CSID_X86_KVM_CLK, not to the clocksource itself any more. There are no remaining users of the clocksource export. Therefore, make the clocksource static again. Signed-off-by: Peter Hilber <peter.hilber@opensynergy.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240201010453.2212371-9-peter.hilber@opensynergy.com
2024-02-07treewide: Remove system_counterval_t.cs, which is never readPeter Hilber
The clocksource pointer in struct system_counterval_t is not evaluated any more. Remove the code setting the member, and the member itself. Signed-off-by: Peter Hilber <peter.hilber@opensynergy.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240201010453.2212371-8-peter.hilber@opensynergy.com
2024-02-07x86/kvm, ptp/kvm: Add clocksource ID, set system_counterval_t.cs_idPeter Hilber
Add a clocksource ID for the x86 kvmclock. Also, for ptp_kvm, set the recently added struct system_counterval_t member cs_id to the clocksource ID (x86 kvmclock or ARM Generic Timer). In the future, get_device_system_crosststamp() will compare the clocksource ID in struct system_counterval_t, rather than the clocksource. For now, to avoid touching too many subsystems at once, extract the clocksource ID from the clocksource. The clocksource dereference will be removed once everything is converted over.. Signed-off-by: Peter Hilber <peter.hilber@opensynergy.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240201010453.2212371-5-peter.hilber@opensynergy.com
2024-02-07x86/tsc: Add clocksource ID, set system_counterval_t.cs_idPeter Hilber
Add a clocksource ID for TSC and a distinct one for the early TSC. Use distinct IDs for TSC and early TSC, since those also have distinct clocksource structs. This should help to keep existing semantics when comparing clocksources. Also, set the recently added struct system_counterval_t member cs_id to the TSC ID in the cases where the clocksource member is being set to the TSC clocksource. In the future, get_device_system_crosststamp() will compare the clocksource ID in struct system_counterval_t, rather than the clocksource. For the x86 ART related code, system_counterval_t.cs == NULL corresponds to system_counterval_t.cs_id == CSID_GENERIC (0). Signed-off-by: Peter Hilber <peter.hilber@opensynergy.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240201010453.2212371-4-peter.hilber@opensynergy.com
2024-02-07x86/tsc: Correct kernel-doc notationRandy Dunlap
Add or modify function descriptions to remove kernel-doc warnings: tsc.c:655: warning: missing initial short description on line: * native_calibrate_tsc tsc.c:1339: warning: Excess function parameter 'cycles' description in 'convert_art_ns_to_tsc' tsc.c:1339: warning: Excess function parameter 'cs' description in 'convert_art_ns_to_tsc' tsc.c:1373: warning: Function parameter or member 'work' not described in 'tsc_refine_calibration_work' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20231221033620.32379-1-rdunlap@infradead.org
2024-02-07KVM: VMX: Report up-to-date exit qualification to userspaceChao Gao
Use vmx_get_exit_qual() to read the exit qualification. vcpu->arch.exit_qualification is cached for EPT violation only and even for EPT violation, it is stale at this point because the up-to-date value is cached later in handle_ept_violation(). Fixes: 70bcd708dfd1 ("KVM: vmx: expose more information for KVM_INTERNAL_ERROR_DELIVERY_EV exits") Signed-off-by: Chao Gao <chao.gao@intel.com> Link: https://lore.kernel.org/r/20231229022652.300095-1-chao.gao@intel.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-02-07ARM: dts: samsung: exynos5420-galaxy-tab-common: add wifi nodeHenrik Grimler
By using brcm/brcmfmac4354-sdio.bin from linux-firmware together with nvram.txt from vendor firmware wifi works well on the chagall-wifi and klimt-lte. Signed-off-by: Henrik Grimler <henrik@grimler.se> Link: https://lore.kernel.org/r/20240206-galaxy-tab-s-cleanup-v2-1-89025c6c66c5@grimler.se Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-02-06arm64: dts: qcom: sc8280xp: Introduce additional tsens instancesBjorn Andersson
The SC8280XP contains two additional tsens instances, providing among other things thermal measurements for the GPU. Add these and a GPU thermal-zone. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240206-sc8280xp-tsens2_3-v3-1-4577b3b38ea8@quicinc.com [bjorn: s/cpu-crit/gpu-crit/] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06riscv: Flush the tlb when a page directory is freedAlexandre Ghiti
The riscv privileged specification mandates to flush the TLB whenever a page directory is modified, so add that to tlb_flush(). Fixes: c5e9b2c2ae82 ("riscv: Improve tlb_flush()") Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240128120405.25876-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-06arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mappingNeil Armstrong
Starting from SM8550, the TX ADC input soundwire port is offset by 1, and uses the new SWR_INPUTx input ports, so replace the legacy SWR_ADCx routes for SWR_INPUT0 & SWR_INPUT1 following the correct TX Soundwire port mapping. Add some comments on the routing for clarity. Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240201-topic-sm8550-hdk8550-audio-fix-v1-1-aa526c9c91d5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8650 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-17-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8550: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8550 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") Reviewed-by: Can Guo <quic_cang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-16-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8350: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-15-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sc8280xp: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SC8280XP requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-14-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sc8180x: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SC8180X requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-13-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07Revert "parisc: Only list existing CPUs in cpu_possible_mask"Helge Deller
This reverts commit 0921244f6f4f0d05698b953fe632a99b38907226. It broke CPU hotplugging because it modifies the __cpu_possible_mask after bootup, so that it will be different than nr_cpu_ids, which then effictively breaks the workqueue setup code and triggers crashes when shutting down CPUs at runtime. Guenter was the first who noticed the wrong values in __cpu_possible_mask, since the cpumask Kunit tests were failig. Reverting this commit fixes both issues, but sadly brings back this uncritical runtime warning: register_cpu_capacity_sysctl: too early to get CPU4 device! Signed-off-by: Helge Deller <deller@gmx.de> Reported-by: Guenter Roeck <linux@roeck-us.net> Link: https://lkml.org/lkml/2024/2/4/146 Link: https://lore.kernel.org/lkml/Zb0mbHlIud_bqftx@slm.duckdns.org/t/ Cc: stable@vger.kernel.org # 6.0+
2024-02-06arm64: dts: qcom: sm8250: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8250 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-12-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8150: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM8150 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 3834a2e92229 ("arm64: dts: qcom: sm8150: Add ufs nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-11-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm6350: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM6350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-10-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm6125: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM6125 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: f8399e8a2f80 ("arm64: dts: qcom: sm6125: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-9-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm6115: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SM6115 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-8-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sdm845: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in SDM845 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: cc16687fbd74 ("arm64: dts: qcom: sdm845: add UFS controller") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-7-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: msm8998: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in MSM8998 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: cd3dbe2a4e6c ("arm64: dts: qcom: msm8998: Add UFS nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-6-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: msm8996: Fix UFS PHY clocksManivannan Sadhasivam
QMP PHY used in MSM8996 requires 2 clocks: * ref - 19.2MHz reference clock from RPM * qref - QREF clock from GCC Fixes: 27520210e881 ("arm64: dts: qcom: msm8996: Use generic QMP driver for UFS") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-5-58a49d2f4605@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: ipq8074: add clock-frequency to MDIO nodeChristian Marangi
Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead of using the default value of 390KHz from MDIO default divider. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240131022731.2118-1-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: qrb2210-rb1: disable cluster power domainsDmitry Baryshkov
If cluster domain idle state is enabled on the RB1, the board becomes significantly less responsive. Under certain circumstances (if some of the devices are disabled in kernel config) the board can even lock up. It seems this is caused by the MPM not updating wakeup timer during CPU idle (in the same way the RPMh updates it when cluster idle state is entered). Disable cluster domain idle for the RB1 board until MPM driver is fixed to cooperate with the CPU idle states. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240130-rb1-suspend-cluster-v2-1-5bc1109b0869@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: msm8953: Add GPUVladimir Lypak
Add the GPU node for the Adreno 506 found on this family of SoCs. The clock speeds are a bit different per SoC variant, SDM450 maxes out at 600MHz while MSM8953 (= SDM625) goes up to 650MHz and SDM632 goes up to 725MHz. To achieve this, create a new sdm450.dtsi to hold the 600MHz OPP and use the new dtsi for sdm450-motorola-ali. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Co-developed-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240125-msm8953-gpu-v1-2-f6493a5951f3@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: msm8953: Add GPU IOMMUVladimir Lypak
Add the IOMMU used for the GPU on MSM8953. Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240125-msm8953-gpu-v1-1-f6493a5951f3@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: msm8953: add reset for display subsystemVladimir Lypak
With this reset we can avoid situations like IRQ storms from DSI host before it even started probing (because boot-loader left DSI IRQs on). Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240125-msm8953-mdss-reset-v2-3-fd7824559426@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650-mtp: add Audio sound card nodeNeil Armstrong
Add the sound card of SM8650-MTP board with the routing for Speakers. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-audio-dt-v1-2-c24d23ae5763@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650-qrd: add Audio nodesNeil Armstrong
Add the remaining Audio nodes on the SM8650-QRD board including: - Qualcomm Aqstic WCD9395 audio codec on the RX & TX Soundwire interfaces - WSA8845 Left & Right Speakers - Link the WCD9395 Codec node to the WCD9395 USB SubSystem node to handle the USB-C Audio Accessory Mode events & lane swapping - Sound card with routing for Speakers and Microphones Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-audio-dt-v1-1-c24d23ae5763@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650: Add dma-coherent propertyLing Xu
Add dma-coherent property to fastRPC context bank nodes to pass dma sequence test in fastrpc sanity test, ensure that data integrity is maintained during DMA operations. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/20240125102413.3016-3-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8550: Add dma-coherent propertyLing Xu
Add dma-coherent property to fastRPC context bank nodes to pass dma sequence test in fastrpc sanity test, ensure that data integrity is maintained during DMA operations. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/20240125102413.3016-2-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650-qrd: add PM8010 regulatorsFenglin Wu
Add PM8010 regulator device nodes for sm8650-qrd board. Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com> Reviewed-by: David Collins <quic_collinsd@quicinc.com> Link: https://lore.kernel.org/r/20240125-sm8650_pm8010_support-v3-2-2f291242a7c4@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8650-mtp: add PM8010 regulatorsFenglin Wu
Add PM8010 regulator device nodes for sm8650-mtp board. Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com> Reviewed-by: David Collins <quic_collinsd@quicinc.com> Link: https://lore.kernel.org/r/20240125-sm8650_pm8010_support-v3-1-2f291242a7c4@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: ipq6018: add thermal zonesMantas Pucka
Add thermal zones to make use of thermal sensors data. For CPU zone, add cooling device that uses CPU frequency scaling. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: ipq6018: add tsens nodeMantas Pucka
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add node for it. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8550-mtp: add correct analogue microphonesKrzysztof Kozlowski
Add proper audio routes for onboard analogue microphones AMIC[1345] - MIC biases and route from TX macro codec to WCD9385 audio codec. This should bring AMIC1, AMIC2 (headphones), AMIC3, AMIC4 and AMIC5 onboard microphones to work, although was not tested on the hardware. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124164505.293202-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8550-qrd: add correct analogue microphonesKrzysztof Kozlowski
Add proper audio routes for onboard analogue microphones AMIC[1345] - MIC biases and route from TX macro codec to WCD9385 audio codec. This finally brings AMIC1, AMIC3, AMIC4 and AMIC5 onboard microphones to work. AMIC2 (headphones) should be fine well, however it didn't work during tests, probably because of incomplete USB switch. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240124164505.293202-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mappingKrzysztof Kozlowski
WCD9385 audio codec TX port mapping was copied form HDK8450, but in fact it is offset by one. Correct it to fix recording via analogue microphones. The change is based on QRD8550 and should be correct here as well, but was not tested on MTP8550. Cc: stable@vger.kernel.org Fixes: a541667c86a9 ("arm64: dts: qcom: sm8550-mtp: add WCD9385 audio-codec") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240124164505.293202-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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