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2024-10-02arm64: dts: mediatek: mt8188: Add PWM nodes for display backlightFei Shao
Add two hardware PWM nodes for display backlight usage on MT8188 SoC, and mark them as disabled by default. Boards can enable the necessary PWM node as needed. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20240911143429.850071-6-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Add SMI/LARB/IOMMU supportFei Shao
Local Arbiter (LARB) is a component of Smart Multimedia Interface (SMI) that supports IOMMU on the MediaTek SoCs. Add the following nodes for memory management support on MT8188 SoC: - one Infra IOMMU - two Multimedia (MM) IOMMUs of VDO and VPP - corresponding SMI common and LARB nodes of the MM IOMMUs Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20240911143429.850071-5-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreqFei Shao
Add performance controller node and performance-domains properties for CPUFreq support on MT8188 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20240911143429.850071-4-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mt8183: Add port node to dpi nodePin-yen Lin
Add the port node to fix the binding schema check. Fixes: 009d855a26fd ("arm64: dts: mt8183: add dpi node to mt8183") Signed-off-by: Pin-yen Lin <treapking@chromium.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202409110843.Hm5W9upr-lkp@intel.com/ Link: https://lore.kernel.org/r/20240912144430.3161717-3-treapking@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mt8192-asurada-spherion: Add Synaptics trackpad supportPin-yen Lin
Some spherion variants use Synaptics trackpad at address 0x2c in the I2C2 bus with the generic HID-over-i2c driver, and this cannot be distinguished from the firmware compatible string. Support both trackpads in the same devicetree by moving the trackpad pinctrl property to i2c2 and adding the node for Synaptics trackpad. Signed-off-by: Pin-yen Lin <treapking@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20240912154451.3447081-1-treapking@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8186: add FHCTL nodemax_weng
add FHCTL device node for Frequency Hopping and Spread Spectrum clock function. Signed-off-by: Max Weng <max_weng@compal.corp-partner.google.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240924101559.879167-1-max_weng@compal.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8183-pumpkin: add HDMI supportFabien Parent
The MT8183 Pumpkin board has a micro-HDMI connector. HDMI support is provided by an IT66121 DPI <-> HDMI bridge. Enable the DPI and add the node for the IT66121 bridge. Signed-off-by: Fabien Parent <fparent@baylibre.com> Co-developed-by: Pin-yen Lin <treapking@chromium.org> Signed-off-by: Pin-yen Lin <treapking@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240919094212.1902073-1-treapking@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8183-kukui: Disable DPI display interfaceAlper Nebi Yasak
Commit 009d855a26fd ("arm64: dts: mt8183: add dpi node to mt8183") adds a device-tree node for the DPI display interface that feeds the external display pipeline, to enable HDMI support on the Pumpkin board. However, the external display is not fully described on Chrome devices, blocked by further work on DP / USB-C muxing graph bindings. This incomplete description currently breaks internal display at least on the Cozmo board. The same issue was found and fixed on MT8186 devices with commit 3079fb09ddac ("arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface"), but the MT8183 change wasn't merged until then. Disable the external display interface for the Kukui device family until the necessary work is done, like in the MT8186 Corsola case. Fixes: 009d855a26fd ("arm64: dts: mt8183: add dpi node to mt8183") Link: https://lore.kernel.org/linux-mediatek/20240821042836.2631815-1-wenst@chromium.org/ Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Pin-yen Lin <treapking@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240916162956.267340-1-alpernebiyasak@gmail.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao nodeMacpaul Lin
The infracfg_ao node in mt8195.dtsi was causing a dtbs_check error. The error message was: syscon@10001000: compatible: ['mediatek,mt8195-infracfg_ao', 'syscon', 'simple-mfd'] is too long To resolve this, remove 'simple-mfd' from the 'compatible' property of the infracfg_ao node. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241002051620.2050-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mt8195: Fix dtbs_check error for mutex nodeMacpaul Lin
The mutex node in mt8195.dtsi was triggering a dtbs_check error: mutex@1c101000: 'clock-names', 'reg-names' do not match any of the regexes: 'pinctrl-[0-9]+' This seems no need by inspecting the DT schemas and other reference boards, so drop 'clock-names' and 'reg-names' in mt8195.dtsi. Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241002051620.2050-4-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phyMacpaul Lin
The ethernet-phy node in mt8395-genio-1200-evk.dts was triggering a dtbs_check error. The error message was: eth-phy0@1: $nodename:0: 'eth-phy0@1' does not match '^ethernet-phy(@[a-f0-9]+)?$' Fix this issue by replacing 'eth-phy' node to generic 'ethernet-phy'. Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241002051620.2050-3-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Move SPI NOR *-cells propertiesFei Shao
Move the #address-cells and #size-cells properties from the board dts to SoC dtsi to be reused by other boards and avoid duplicated lines. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241001113052.3124869-9-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0Fei Shao
The MT8188 video decoder pipeline has two hardware IP blocks: LAT and Core, which are powered by vdec0 and vdec1 power domains, respectively. The hardware design includes a dependency between the vdec0 and vdec1 power domains to ensure that Core is powered down before LAT. Without correctly describing this dependency in DT, the system will fail to suspend. As a comparable reference, MT8192 also uses the LAT + Core decoding pipeline, and it has the correct power domain dependency defined in DT. Update vdec1 as a sub-domain of vdec0 in MT8188 DT to reflect the hardware design. Also, use more specific clock names for both power domains. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241001113052.3124869-8-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Update vppsys node names to sysconFei Shao
The MediaTek mmsys is more than just a clock controller; it's a system controller. In addition to clock controls, it provides display pipeline routing controls and other miscellaneous control registers. On the MT8188 and MT8195 SoCs, the mmsys blocks utilize the same mmsys driver but have been aliased to "vdosys" and "vppsys", likely to better represent their actual functionality. Update the vppsys node names and compatibles in MT8188 DT to reflect that and fix dtbs_check errors against mediatek/mt8188-evb.dtb. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241001113052.3124869-7-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc nodeFei Shao
Add the missing dma-ranges property to the soc node, similar to how it was done for MT8195 and MT8192. This allows the entire 16GB of iova range to be used and enables multimedia processing usages, like vcodec and MIPI camera. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241001113052.3124869-6-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPUPablo Sun
Configure GPU regulator supplies and enable GPU for GENIO 700 EVK. The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and "DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by mt6359_vsram_others_ldo_reg. According to section 5.2 "Recommended Operating Conditions" in MT8390 IoT Application Processor Datasheet v1.9, The recommended operating voltage ranges are: - DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V - DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V To further optimize power saving, we couple DVDD_SRAM_GPU to DVDD_GPU according to the following relation: - For opp-880000000 or lower frequency, keep 0.75V - For opp-915000000 and higher, DVDD_SRAM_GPU should follow DVDD_GPU. The exact voltage for DVDD_GPU should be decided by speed binning. This rule is derived from the OPP table in the link. In addition, set the voltage spread to 6250 uV, the step size of 'ldo_vsram_others' regulator of mt6359, otherwise the regulator set_voltage operation fails. Link: https://gitlab.com/mediatek/aiot/rity/meta-mediatek-bsp/-/blob/eedd6aedd4b0cfc0ee79b9c9b9650dfa73cf87f6/recipes-kernel/dtbo/mt8390/gpu-mali.dts Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241002022138.29241-7-pablo.sun@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domainPablo Sun
The clock index "CLK_APMIXED_MFGPLL" belongs to the "apmixedsys" provider, so fix the index. In addition, add a "mfg1" label so following commits could set domain-supply for MFG1 power domain. Fixes: eaf73e4224a3 ("arm64: dts: mediatek: mt8188: Add support for SoC power domains") Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241002022138.29241-2-pablo.sun@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-02arm64: dts: rockchip: Enable all 3 USBs on Turing RK1Sam Edwards
The Turing RK1 contains 3 different USBs: - USB0: USB 2.0, OTG - USB1: USB 3.0, host - USB2: USB 2.0, host This patch activates the necessary DT nodes to enable all 3 buses. Future work will be needed on USB0: it is not USB3-capable, so the USB0 controller needs to be told that there is no USB3 port. Per Jonas's suggestion, the USBDP0 node is given a `rockchip,dp-lane-mux` property that tells the USBDP driver that USBDP0 is not involved in USB so that it can make the necessary configuration changes in hardware. Technically, this is USB *controller* configuration, not *PHY* configuration, so the underlying code may be moved in the future to the USB controller driver instead, freeing up the (software) dependency on USBDP0. A TODO comment is added to explain this. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Suggested-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240930210652.1232951-1-CFSworks@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-02arm64: dts: rockchip: Add Powkiddy RGB20SXChris Morgan
The Powkiddy RGB20SX is a portable game console extremely similar to the existing RGB30 console. The key differences from the RGB30 are as follows: - Realtek RTW8723DS WiFi and Bluetooth. - UART pads for debug console (UART2). - A function button (ADC channel 0). - A much larger battery (5000 mAh). Otherwise, the device is identical to the RGB30, including the hard-coded value on ADC channel 1 used to identify the device at runtime. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20241001154016.87386-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-02arm64: dts: rockchip: Add power button for puma-haikouDaniel Semkowicz
There is a PWRBTN# input pin exposed on a Q7 connector. The pin is routed to a GPIO0_A1 through a diode. Q7 specification describes the PWRBTN# pin as a Power Button signal. Configure the pin as KEY_POWER, so it can function as power button and trigger device shutdown. Signed-off-by: Daniel Semkowicz <dse@thaumatec.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20241001134741.210979-1-dse@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-02arm64: dts: exynos: Add initial support for Samsung Galaxy S8Ivaylo Ivanov
Samsung Galaxy S8 (SM-G950F), codenamed dreamlte, is a mobile phone from 2017. It features 4GB RAM, 64GB UFS 2.1, Exynos 8895 SoC and a 1440x2960 Super AMOLED display. This initial device tree enables SimpleFB, PSTORE and GPIO keys. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20240920154508.1618410-11-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-02arm64: dts: exynos: Add initial support for exynos8895 SoCIvaylo Ivanov
Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu 15 Plus (m1891). Add minimal support for that SoC, including: - All 8 cores via PSCI - ChipID - Generic ARMV8 Timer - Enumarate all pinctrl nodes The devices using this SoC suffer from an issue caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Further platform support will be added over time. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20240920154508.1618410-9-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-02arm64: zynqmp: Add thermal zonesSean Anderson
Add some thermal trip points. We can't undervolt the CPUs to save power when we underclock them, so there isn't really a point in throttling them until we are about to overheat. As such, the passive trip point is right below the critical trip point. The critical trip point is the extended/industrial-grade maximum junction temperature of 100C minus the maximum temperature sensor error of 3.5C (in the range -55C to 110C). Automotive- and military-grade parts can go up to 125C, but as far as I can tell there is no way to detect them at runtime. Userspace can adjust the trip points at runtime, but this may not be viable when booting above 100C. I think it's reasonable to ask automotive/military users to edit their device trees to bump the trip points, but if that proves to be an issue we can always go with no default temperatures. However, that wouldn't be too nice for the majority of extended/industrial users. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240812215129.3599832-4-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-10-02arm64: zynqmp: Expose AMS to userspace as HWMONSean Anderson
Expose the AMS to userspace, allowing monitoring of internal voltages and temperatures. For compatibility, we keep the node name the same as on the SM-K26, and we keep the ZCU100 Rev C. around (since it is named differently). Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240812215129.3599832-3-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-10-02arm64: zynqmp: Enable AMS for all boardsSean Anderson
The AMS does not rely on external hardware or features, so it can be enabled unconditionally. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240812215129.3599832-2-sean.anderson@linux.dev Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-10-02microblaze: Export xmb_manager functionsMichal Simek
When TMR_MANAGER is enabled as module there is a need to export functions which are present in architecture code. It has been found by running: make W=1 C=1 allmodconfig sed -i -e 's/WERROR=y/WERROR=n/g' .config make C=1 W=1 which errors out like this: ERROR: modpost: "xmb_manager_register" [drivers/misc/xilinx_tmr_manager.ko] undefined! ERROR: modpost: "xmb_inject_err" [drivers/misc/xilinx_tmr_inject.ko] undefined! Fixes: a5e3aaa654c1 ("microblaze: Add xmb_manager_register function") Reported-by: Jeff Johnson <quic_jjohnson@quicinc.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e322dbbbde0feef83f44304ea13249d365d1dc5f.1718799090.git.michal.simek@amd.com
2024-10-02ARM: zynq: Remove unused zynq_slcr_init() declarationGaosheng Cui
The zynq_slcr_init() has been removed since commit 3329659df030 ("ARM: zynq: Simplify SLCR initialization"), so remove it. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Link: https://lore.kernel.org/r/20240813103556.1138061-1-cuigaosheng1@huawei.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-10-01parisc: get rid of private asm/unaligned.hAl Viro
Declarations local to arch/*/kernel/*.c are better off *not* in a public header - arch/parisc/kernel/unaligned.h is just fine for those bits. With that done parisc asm/unaligned.h is reduced to include of asm-generic/unaligned.h and can be removed - unaligned.h is in mandatory-y in include/asm-generic/Kbuild. Acked-by: Helge Deller <deller@gmx.de> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2024-10-01ARM: dts: socfpga: Fix at24 EEPROM node namesRob Herring (Arm)
at24.yaml defines the node name for at24 EEPROMs as 'eeprom'. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-10-01riscv: Fix kernel stack size when KASAN is enabledAlexandre Ghiti
We use Kconfig to select the kernel stack size, doubling the default size if KASAN is enabled. But that actually only works if KASAN is selected from the beginning, meaning that if KASAN config is added later (for example using menuconfig), CONFIG_THREAD_SIZE_ORDER won't be updated, keeping the default size, which is not enough for KASAN as reported in [1]. So fix this by moving the logic to compute the right kernel stack into a header. Fixes: a7555f6b62e7 ("riscv: stack: Add config of thread stack size") Reported-by: syzbot+ba9eac24453387a9d502@syzkaller.appspotmail.com Closes: https://lore.kernel.org/all/000000000000eb301906222aadc2@google.com/ [1] Cc: stable@vger.kernel.org Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240917150328.59831-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-10-01KVM: arm64: Constrain the host to the maximum shared SVE VL with pKVMMark Brown
When pKVM saves and restores the host floating point state on a SVE system, it programs the vector length in ZCR_EL2.LEN to be whatever the maximum VL for the PE is. But it uses a buffer allocated with kvm_host_sve_max_vl, the maximum VL shared by all PEs in the system. This means that if we run on a system where the maximum VLs are not consistent, we will overflow the buffer on PEs which support larger VLs. Since the host will not currently attempt to make use of non-shared VLs, fix this by explicitly setting the EL2 VL to be the maximum shared VL when we save and restore. This will enforce the limit on host VL usage. Should we wish to support asymmetric VLs, this code will need to be updated along with the required changes for the host: https://lore.kernel.org/r/20240730-kvm-arm64-fix-pkvm-sve-vl-v6-0-cae8a2e0bd66@kernel.org Fixes: b5b9955617bc ("KVM: arm64: Eagerly restore host fpsimd/sve state in pKVM") Signed-off-by: Mark Brown <broonie@kernel.org> Tested-by: Fuad Tabba <tabba@google.com> Reviewed-by: Fuad Tabba <tabba@google.com> Link: https://lore.kernel.org/r/20240912-kvm-arm64-limit-guest-vl-v2-1-dd2c29cb2ac9@kernel.org [maz: added punctuation to the commit message] Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-10-01KVM: arm64: Fix __pkvm_init_vcpu cptr_el2 error pathVincent Donnefort
On an error, hyp_vcpu will be accessed while this memory has already been relinquished to the host and unmapped from the hypervisor. Protect the CPTR assignment with an early return. Fixes: b5b9955617bc ("KVM: arm64: Eagerly restore host fpsimd/sve state in pKVM") Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Signed-off-by: Vincent Donnefort <vdonnefort@google.com> Link: https://lore.kernel.org/r/20240919110500.2345927-1-vdonnefort@google.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-10-01ARM: dts: renesas: rskrza1: Enable watchdog timerGeert Uytterhoeven
Enable the Watchdog Timer (WDT) on the Renesas RSK+RZA1 development board equipped with an RZ/A1H SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/fe72fb72acde4f5d9f8bd1a012435519592bd2bc.1727441772.git.geert+renesas@glider.be
2024-10-01arm64: dts: renesas: rcar-gen4: Switch PCIe to reset-gpiosGeert Uytterhoeven
Commit 42694f9f6407a933 ("dt-bindings: PCI: add snps,dw-pcie.yaml") deprecated the "reset-gpio" property in favor of "reset-gpios". Hence replace the "reset-gpio" property by "reset-gpios" in PCIe device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/853019acdfcdf05fcb46d8124157ef298da55188.1727438172.git.geert+renesas@glider.be
2024-10-01ARM: dts: renesas: rza2mevb: Use interrupts-extended for gpio-keysWolfram Sang
Use the more concise interrupts-extended property to fully describe the interrupt. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240927095414.10241-10-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: rskrza1: Use interrupts-extended for gpio-keysWolfram Sang
Use the more concise interrupts-extended property to fully describe the interrupt. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240927095414.10241-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: marzen: Use interrupts-extended for gpio-keysWolfram Sang
Using the inherited interrupt-parent is discouraged. Use interrupts-extended to fully describe the interrupt. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240927095414.10241-7-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: Remove 'reg-io-width' properties from MMCIF nodesWolfram Sang
The driver does not use this property and all upstream SoCs use the same value anyhow. Remove it and get rid of a lot of dtbs_check warnings. Tested with a Lager (R-Car H2) board and with the soon to be added Genmai (RZA1) MMCIF support. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240925150904.3582-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: Genmai: Update audio codec device nodeWolfram Sang
Meanwhile, bindings for the audio codec exist. Add #sound-dai-cells property and limit max frequency accordingly. codec@0: '#sound-dai-cells' is a required property codec@0: spi-max-frequency: 5000000 is greater than the maximum of 526000 Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240925090812.14497-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: genmai: Define keyboard switchWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240921114813.4124-12-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/20240927095414.10241-8-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: genmai: Sort nodesWolfram Sang
To make future additions easier. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240921114813.4124-10-wsa+renesas@sang-engineering.com Link: https://lore.kernel.org/20240921114813.4124-11-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: genmai: Enable OS timer modulesWolfram Sang
Driver has been submitted meanwhile. Activate the devices. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240921114813.4124-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: genmai: Enable watchdogWolfram Sang
Driver has been submitted meanwhile. Activate the device. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240921114813.4124-8-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: dts: renesas: genmai: Fix partition size for QSPI NOR FlashWolfram Sang
Second partition was too large, looks like two digits got mixed up. Fixes: mtd: partition "user1" extends beyond the end of device "18000000.flash" -- size truncated to 0x4000000 Fixes: 30e0a8cf886c ("ARM: dts: renesas: genmai: Add FLASH nodes") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240914182948.94031-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01arm64: dts: renesas: r8a779h0: gray-hawk-single: Enable PCIe HostYoshihiro Shimoda
Enable PCIe Host controller on R-Car V4M Gray Hawk board. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240904003409.1578212-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01arm64: dts: renesas: r8a779h0: Add PCIe Host and Endpoint nodesYoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car V4M (R8A779H0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240904003409.1578212-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01ARM: imx: Allow user to disable pinctrlEsben Haabendal
Making pinctrl drivers and subsequently the pinctrl framework user-controllable, allows building a kernel without this. While in many (most) cases, this could make the system unbootable, it does allow building smaller kernels for those situations where picntrl is not needed. One such situation is when building a kernel for NXP LS1021A systems, which does not have run-time controllable pinctrl, so pinctrl framework and drivers are 100% dead-weight. Signed-off-by: Esben Haabendal <esben@geanix.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240506-imx-pinctrl-optional-v2-1-bdff75085156@geanix.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-10-01arm64: fix selection of HAVE_DYNAMIC_FTRACE_WITH_ARGSMark Rutland
The Kconfig logic to select HAVE_DYNAMIC_FTRACE_WITH_ARGS is incorrect, and HAVE_DYNAMIC_FTRACE_WITH_ARGS may be selected when it is not supported by the combination of clang and GNU LD, resulting in link-time errors: aarch64-linux-gnu-ld: .init.data has both ordered [`__patchable_function_entries' in init/main.o] and unordered [`.meminit.data' in mm/sparse.o] sections aarch64-linux-gnu-ld: final link failed: bad value ... which can be seen when building with CC=clang using a binutils version older than 2.36. We originally fixed that in commit: 45bd8951806eb5e8 ("arm64: Improve HAVE_DYNAMIC_FTRACE_WITH_REGS selection for clang") ... by splitting the "select HAVE_DYNAMIC_FTRACE_WITH_ARGS" statement into separete CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS and GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS options which individually select HAVE_DYNAMIC_FTRACE_WITH_ARGS. Subsequently we accidentally re-introduced the common "select HAVE_DYNAMIC_FTRACE_WITH_ARGS" statement in commit: 26299b3f6ba26bfc ("ftrace: arm64: move from REGS to ARGS") ... then we removed it again in commit: 68a63a412d18bd2e ("arm64: Fix build with CC=clang, CONFIG_FTRACE=y and CONFIG_STACK_TRACER=y") ... then we accidentally re-introduced it again in commit: 2aa6ac03516d078c ("arm64: ftrace: Add direct call support") Fix this for the third time by keeping the unified select statement and making this depend onf either GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS or CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS. This is more consistent with usual style and less likely to go wrong in future. Fixes: 2aa6ac03516d ("arm64: ftrace: Add direct call support") Cc: <stable@vger.kernel.org> # 6.4.x Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240930120448.3352564-1-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-01arm64: errata: Expand speculative SSBS workaround once moreMark Rutland
A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We worked around this for a number of CPUs in commits: * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") * 145502cac7ea70b5 ("arm64: errata: Expand speculative SSBS workaround (again)") Since then, a (hopefully final) batch of updates have been published, with two more affected CPUs. For the affected CPUs the existing mitigation is sufficient, as described in their respective Software Developer Errata Notice (SDEN) documents: * Cortex-A715 (MP148) SDEN v15.0, erratum 3456084 https://developer.arm.com/documentation/SDEN-2148827/1500/ * Neoverse-N3 (MP195) SDEN v5.0, erratum 3456111 https://developer.arm.com/documentation/SDEN-3050973/0500/ Enable the existing mitigation by adding the relevant MIDRs to erratum_spec_ssbs_list, and update silicon-errata.rst and the Kconfig text accordingly. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240930111705.3352047-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-01arm64: cputype: Add Neoverse-N3 definitionsMark Rutland
Add cputype definitions for Neoverse-N3. These will be used for errata detection in subsequent patches. These values can be found in Table A-261 ("MIDR_EL1 bit descriptions") in issue 02 of the Neoverse-N3 TRM, which can be found at: https://developer.arm.com/documentation/107997/0000/?lang=en Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240930111705.3352047-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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