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2024-10-06arm64: dts: qcom: sdm630: enable A2NOC and LPASS SMMUDmitry Baryshkov
Now as the arm-smmu-qcom driver gained workarounds for the A2NOC and LPASS SMMU devices, enable those two devices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-5-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sda660-ifc6560: fix l10a voltage rangesDmitry Baryshkov
L10A, being a fixed regulator, should have min_voltage = max_voltage, otherwise fixed rulator fails to probe. Fix the max_voltage range to be equal to minimum. Fixes: 4edbcf264fe2 ("arm64: dts: qcom: sda660-ifc6560: document missing USB PHY supplies") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-4-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sda660-ifc6560: enable GPUDmitry Baryshkov
Enable Adreno GPU on the Inforce IFC6560 SBC. It requires the Zap shader binary that was provided by the vendor. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-3-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCCDmitry Baryshkov
Now as the arm-smmu-qcom driver gained workarounds for the Adreno SMMU, it becomes possible to safely enable GPU on the devices. Enable GPU SMMU and GPU clock controller. GPU should be enabled for target devices that have ZAP shader blob. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240907-sdm660-wifi-v1-2-e316055142f8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-06Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm fixes from Paolo Bonzini: "ARM64: - Fix pKVM error path on init, making sure we do not change critical system registers as we're about to fail - Make sure that the host's vector length is at capped by a value common to all CPUs - Fix kvm_has_feat*() handling of "negative" features, as the current code is pretty broken - Promote Joey to the status of official reviewer, while James steps down -- hopefully only temporarly x86: - Fix compilation with KVM_INTEL=KVM_AMD=n - Fix disabling KVM_X86_QUIRK_SLOT_ZAP_ALL when shadow MMU is in use Selftests: - Fix compilation on non-x86 architectures" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: x86/reboot: emergency callbacks are now registered by common KVM code KVM: x86: leave kvm.ko out of the build if no vendor module is requested KVM: x86/mmu: fix KVM_X86_QUIRK_SLOT_ZAP_ALL for shadow MMU KVM: arm64: Fix kvm_has_feat*() handling of negative features KVM: selftests: Fix build on architectures other than x86_64 KVM: arm64: Another reviewer reshuffle KVM: arm64: Constrain the host to the maximum shared SVE VL with pKVM KVM: arm64: Fix __pkvm_init_vcpu cptr_el2 error path
2024-10-06Merge tag 'powerpc-6.12-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fix from Michael Ellerman: - Allow r30 to be used in vDSO code generation of getrandom Thanks to Jason A. Donenfeld * tag 'powerpc-6.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/vdso: allow r30 in vDSO code generation of getrandom
2024-10-06Merge tag 'kvmarm-fixes-6.12-1' of ↵Paolo Bonzini
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 6.12, take #1 - Fix pKVM error path on init, making sure we do not change critical system registers as we're about to fail - Make sure that the host's vector length is at capped by a value common to all CPUs - Fix kvm_has_feat*() handling of "negative" features, as the current code is pretty broken - Promote Joey to the status of official reviewer, while James steps down -- hopefully only temporarly
2024-10-06x86/reboot: emergency callbacks are now registered by common KVM codePaolo Bonzini
Guard them with CONFIG_KVM_X86_COMMON rather than the two vendor modules. In practice this has no functional change, because CONFIG_KVM_X86_COMMON is set if and only if at least one vendor-specific module is being built. However, it is cleaner to specify CONFIG_KVM_X86_COMMON for functions that are used in kvm.ko. Reported-by: Linus Torvalds <torvalds@linux-foundation.org> Fixes: 590b09b1d88e ("KVM: x86: Register "emergency disable" callbacks when virt is enabled") Fixes: 6d55a94222db ("x86/reboot: Unconditionally define cpu_emergency_virt_cb typedef") Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-06KVM: x86: leave kvm.ko out of the build if no vendor module is requestedPaolo Bonzini
kvm.ko is nothing but library code shared by kvm-intel.ko and kvm-amd.ko. It provides no functionality on its own and it is unnecessary unless one of the vendor-specific module is compiled. In particular, /dev/kvm is not created until one of kvm-intel.ko or kvm-amd.ko is loaded. Use CONFIG_KVM to decide if it is built-in or a module, but use the vendor-specific modules for the actual decision on whether to build it. This also fixes a build failure when CONFIG_KVM_INTEL and CONFIG_KVM_AMD are both disabled. The cpu_emergency_register_virt_callback() function is called from kvm.ko, but it is only defined if at least one of CONFIG_KVM_INTEL and CONFIG_KVM_AMD is provided. Fixes: 590b09b1d88e ("KVM: x86: Register "emergency disable" callbacks when virt is enabled") Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-05arm64: dts: qcom: qcm6490-fairphone-fp5: Add thermistor for UFS/RAMLuca Weiss
Configure the ADC and thermal zone for the thermistor next to the UFS+RAM chip which is connected to GPIO_12 of PM7250B. It is used to measure the temperature of that area of the PCB. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20241002-fp5-ufs-therm-v1-1-1d2d8c1f08b5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbinsLuca Weiss
Make sure the GPU frequencies are marked as supported for the respective speedbins according to downstream msm-4.19 kernel: * 850 MHz: Speedbins 0 + 180 * 800 MHz: Speedbins 0 + 180 + 169 * 650 MHz: Speedbins 0 + 180 + 169 + 138 * 565 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 430 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 355 MHz: Speedbins 0 + 180 + 169 + 138 + 120 * 253 MHz: Speedbins 0 + 180 + 169 + 138 + 120 Fixes: bd9b76750280 ("arm64: dts: qcom: sm6350: Add GPU nodes") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20241002-sm6350-gpu-speedbin-fix-v1-1-8a5d90c5097d@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5GJérôme de Bretagne
Add an initial devicetree for the Microsoft Surface Pro 9 5G, based on SC8280XP. It enables the support for Wi-Fi, NVMe, the two USB Type-C ports, Bluetooth, 5G cellular modem, audio output (via Bluetooth headsets or USB audio), external display via DisplayPort over Type-C (only the bottom USB Type-C port is working so far), charging, the Surface Aggregator Module (SAM) to get keyboard and touchpad working with Surface Type Cover accessories. Some key features not supported yet: - built-in display (but software fallback is working with efifb when blacklisting the msm module) - built-in display touchscreen - external display with the top USB Type-C port - speakers and microphones - physical volume up and down keys - LID switch detection This devicetree is based on the other SC8280XP ones, for the Lenovo ThinkPad X13s and the Qualcomm CRD. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20240908223505.21011-6-jerome.debretagne@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc8280xp: Add uart18Jérôme de Bretagne
Add the node describing uart18 for sc8280xp devices. Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com> Link: https://lore.kernel.org/r/20240908223505.21011-5-jerome.debretagne@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-4-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: drop underscore in node namesKrzysztof Kozlowski
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-3-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05ARM: dts: qcom: minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-2-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05ARM: dts: qcom: drop underscore in node namesKrzysztof Kozlowski
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for avago,apds9930 node, because generic naming is favored by Devicetree spec. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-1-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100-romulus: Set up USB Multiport controllerKonrad Dybcio
The USB MP controller is wired up to the USB-A port on the left side and to the Surface Connector on the right side. Configure it. While at it, remove a stray double \n. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-2-3ee667e6652d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100-romulus: Add lid switchKonrad Dybcio
One of the best parts of having a laptop is being able to close the lid and go on with your day. Enable this feature by defining the lid switch. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240902-topic-sl7_updates-v1-1-3ee667e6652d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc7280: Fix PMU nodes for Cortex A55 and A78Danila Tikhonov
The SC7280, SM7325, and QCM6490 platforms feature an 8-core setup consisting of: - 1x Kryo 670 Prime (Cortex-A78) / Kryo 670 Gold Plus (Cortex-A78) - 3x Kryo 670 Gold (Cortex-A78) - 4x Kryo 670 Silver (Cortex-A55) (The CPU cores in the SC7280 are simply called Kryo, but are nevertheless based on the same Cortex A78 and A55). Use the correct compatibility. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20240818192905.120477-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100: Add debug uart to Lenovo Yoga Slim 7xMaya Matuszczyk
This commit enables the debug UART found on the motherboard under the SSD Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com> Link: https://lore.kernel.org/r/20241004192436.16195-2-maccraft123mc@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100: describe tcsr download mode registerJohan Hovold
Describe the TCSR download mode register to enable download mode control. This specifically allows the OS to disable download mode in case the boot firmware has left it enabled to avoid entering the crash dump mode after a hypervisor reset by default. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241002100122.18809-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100: fix PCIe5 PHY clocksJohan Hovold
Add the missing clkref enable and pipediv2 clocks to the PCIe5 PHY. Fixes: 62ab23e15508 ("arm64: dts: qcom: x1e80100: add PCIe5 nodes") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240916082307.29393-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100: fix PCIe4 and PCIe6a PHY clocksJohan Hovold
Add the missing clkref enable and pipediv2 clocks to the PCIe4 and PCIe6a PHYs. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Cc: stable@vger.kernel.org # 6.9 Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240916082307.29393-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: qcs6460-rb3gen2: enable venus nodeVedang Nagar
Enable the venus node on Qualcomm Rb3gen2 so that the video decoder will start working. Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240917-venus_rb3_gen2-v1-1-8fea70733592@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-11-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-10-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-9-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-8-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4 Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-7-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-6-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-5-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-4-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-3-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-2-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmuKonrad Dybcio
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent pagetable walk via the IDR0 register. This however is not respected by the arm-smmu driver unless dma-coherent is set. Mark the node as dma-coherent to ensure this (and other) implementations take this coherency into account. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp) Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-1-5b3a8662403d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: qcs6490-rb3gen2: Add SD Card nodeSachin Gupta
Add SD Card node for Qualcomm qcs6490-rb3gen2 Board. Signed-off-by: Sachin Gupta <quic_sachgupt@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240919084826.1117-1-quic_sachgupt@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8650-qrd: remove status property from dispcc device tree ↵Vladimir Zapolskiy
node After a change enabling display clock controller for all Qualcomm SM8650 powered board by default there is no more need to set a status property of dispcc on SM8650-QRD board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-10-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8650-mtp: remove status property from dispcc device tree ↵Vladimir Zapolskiy
node After a change enabling display clock controller for all Qualcomm SM8650 powered board by default there is no more need to set a status property of dispcc on SM8650-MTP board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-9-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8650-hdk: remove status property from dispcc device tree ↵Vladimir Zapolskiy
node After a change enabling display clock controller for all Qualcomm SM8650 powered board by default there is no more need to set a status property of dispcc on SM8650-HDK board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-8-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8650: don't disable dispcc by defaultVladimir Zapolskiy
Enable display clock controller for all Qualcomm SM8650 powered boards by default. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-7-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8450-hdk: remove status property from dispcc device tree ↵Vladimir Zapolskiy
node After a change enabling display clock controller for all Qualcomm SM8450 powered board by default there is no more need to set a status property of dispcc on SM8450-HDK board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-6-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8450: don't disable dispcc by defaultVladimir Zapolskiy
Enable display clock controller for all Qualcomm SM8450 powered boards by default. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8450-sony-xperia-nagara: disable dispcc on derived boardsVladimir Zapolskiy
A platform display clock controller is expected to be enabled by default for all boards, however in particular cases preset display clock setting is expected. To avoid any probable regression before enabling display clock controller for all SM8450 platforms disable it for SM8450 powered Sony Xperia phones. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8450-qrd: explicitly disable dispcc on the boardVladimir Zapolskiy
A platform display clock controller is expected to be enabled by default for all boards, however in particular cases preset display clock setting is expected. To avoid any probable regression before enabling display clock controller for all SM8450 platforms disable it for SM8450-QRD board only. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-3-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: sm8350-hdk: remove a blank overwrite of dispcc node statusVladimir Zapolskiy
According to the description of dispcc device tree node from sm8350.dtsi there is no need to set a status property value to enable the display clock controller. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240924100602.3813725-2-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: qcom: msm8998: add HDMI nodesArnaud Vrac
Add HDMI controller and PHY nodes, ported from vendor code. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Link: https://lore.kernel.org/r/20240724-hdmi-tx-v7-6-e44a20553464@freebox.fr [bjorn: Updated commit message] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05arm64: dts: rockchip: Switch to hp-det-gpiosGeert Uytterhoeven
Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio Graph Card and Realtek RT5651 Audio Codec device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-05arm64: dts: rockchip: Switch to simple-audio-card,hp-det-gpiosGeert Uytterhoeven
Replace the deprecated "simple-audio-card,hp-det-gpio" property by "simple-audio-card,hp-det-gpios" in Simple Audio Card device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/c976b09c6048564737321cf91c3f97b9da5dbfe8.1727438777.git.geert+renesas@glider.be Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-10-05riscv: Call riscv_user_isa_enable() only on the boot hartSamuel Holland
Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240814081126.956287-4-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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