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2024-10-17KVM: arm64: Fix shift-out-of-bounds bugIlkka Koskinen
Fix a shift-out-of-bounds bug reported by UBSAN when running VM with MTE enabled host kernel. UBSAN: shift-out-of-bounds in arch/arm64/kvm/sys_regs.c:1988:14 shift exponent 33 is too large for 32-bit type 'int' CPU: 26 UID: 0 PID: 7629 Comm: qemu-kvm Not tainted 6.12.0-rc2 #34 Hardware name: IEI NF5280R7/Mitchell MB, BIOS 00.00. 2024-10-12 09:28:54 10/14/2024 Call trace: dump_backtrace+0xa0/0x128 show_stack+0x20/0x38 dump_stack_lvl+0x74/0x90 dump_stack+0x18/0x28 __ubsan_handle_shift_out_of_bounds+0xf8/0x1e0 reset_clidr+0x10c/0x1c8 kvm_reset_sys_regs+0x50/0x1c8 kvm_reset_vcpu+0xec/0x2b0 __kvm_vcpu_set_target+0x84/0x158 kvm_vcpu_set_target+0x138/0x168 kvm_arch_vcpu_ioctl_vcpu_init+0x40/0x2b0 kvm_arch_vcpu_ioctl+0x28c/0x4b8 kvm_vcpu_ioctl+0x4bc/0x7a8 __arm64_sys_ioctl+0xb4/0x100 invoke_syscall+0x70/0x100 el0_svc_common.constprop.0+0x48/0xf0 do_el0_svc+0x24/0x38 el0_svc+0x3c/0x158 el0t_64_sync_handler+0x120/0x130 el0t_64_sync+0x194/0x198 Fixes: 7af0c2534f4c ("KVM: arm64: Normalize cache configuration") Cc: stable@vger.kernel.org Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20241017025701.67936-1-ilkka@os.amperecomputing.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2024-10-17KVM: arm64: Shave a few bytes from the EL2 idmap codeMarc Zyngier
Our idmap is becoming too big, to the point where it doesn't fit in a 4kB page anymore. There are some low-hanging fruits though, such as the el2_init_state horror that is expanded 3 times in the kernel. Let's at least limit ourselves to two copies, which makes the kernel link again. At some point, we'll have to have a better way of doing this. Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20241009204903.GA3353168@thelio-3990X
2024-10-17arm64: dts: exynos: Add initial support for Samsung Galaxy Note20 5G (c1s)Igor Belwon
Add initial support for the Samsung Galaxy Note20 5G (c1s/SM-N981B) phone. It was launched in 2020, and it's based on the Exynos 990 SoC. It has only one configuration with 8GB of RAM, albeit storage options may differ. This device tree adds support for the following: - SimpleFB - 8GB RAM - Buttons Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241016154747.64343-7-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-17arm64: dts: exynos: Add initial support for the Exynos 990 SoCIgor Belwon
The Exynos 990 SoC is an ARMv8 mobile SoC found in Samsung Galaxy N/S20 series phones (x1sxxx, c1sxxx). Add minimal support for this SoC, including: - All 8 cores via PSCI - ChipID - Generic timer. - Pinctrl The devices using this SoC suffer from the same issue as Exynos 8895 caused by the stock Samsung bootloader, as it doesn't configure CNTFRQ_EL0. Hence it's needed to hardcode the adequate frequency in the timer node, otherwise the kernel panics. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241016154747.64343-6-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-16arm64: dts: qcom: x1e80100: Resize GIC Redistributor register regionSibi Sankar
Resize the GICR register region as it currently seeps into the CPU Control Processor mailbox RX region. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes descriptionAbel Vesa
Fix the description and compatible for PCIe 6a, as it is in fact a 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number of lanes in which the PHY should be configured depends on a TCSR register value on each individual board. Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241009-x1e80100-dts-fixes-pcie6a-v3-1-14a1163e691b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16x86/acpi: Switch to irq_get_nr_irqs() and irq_set_nr_irqs()Bart Van Assche
Use the irq_get_nr_irqs() and irq_set_nr_irqs() functions instead of the global variable 'nr_irqs'. Prepare for changing 'nr_irqs' from an exported global variable into a variable with file scope. Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241015190953.1266194-7-bvanassche@acm.org
2024-10-16s390/irq: Switch to irq_get_nr_irqs()Bart Van Assche
Use the irq_get_nr_irqs() function instead of the global variable 'nr_irqs'. Prepare for changing 'nr_irqs' from an exported global variable into a variable with file scope. Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241015190953.1266194-6-bvanassche@acm.org
2024-10-16powerpc/cell: Switch to irq_get_nr_irqs()Bart Van Assche
Use the irq_get_nr_irqs() function instead of the global variable 'nr_irqs'. Prepare for changing 'nr_irqs' from an exported global variable into a variable with file scope. Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Link: https://lore.kernel.org/all/20241015190953.1266194-5-bvanassche@acm.org
2024-10-16LoongArch: Switch to irq_set_nr_irqs()Bart Van Assche
Use the irq_set_nr_irqs() function instead of the global variable 'nr_irqs'. Prepare for changing 'nr_irqs' from an exported global variable into a variable with file scope. Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241015190953.1266194-4-bvanassche@acm.org
2024-10-16ARM: Switch to irq_get_nr_irqs() / irq_set_nr_irqs()Bart Van Assche
Use the irq_get_nr_irqs() and irq_set_nr_irqs() functions instead of the global variable 'nr_irqs'. Prepare for changing 'nr_irqs' from an exported global variable into a variable with file scope. Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20241015190953.1266194-3-bvanassche@acm.org
2024-10-16virt: sev-guest: Carve out SNP message context structureNikunj A Dadhania
Currently, the sev-guest driver is the only user of SNP guest messaging. The snp_guest_dev structure holds all the allocated buffers, secrets page and VMPCK details. In preparation for adding messaging allocation and initialization APIs, decouple snp_guest_dev from messaging-related information by carving out the guest message context structure(snp_msg_desc). Incorporate this newly added context into snp_send_guest_request() and all related functions, replacing the use of the snp_guest_dev. No functional change. Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20241009092850.197575-7-nikunj@amd.com
2024-10-16virt: sev-guest: Consolidate SNP guest messaging parameters to a structNikunj A Dadhania
Add a snp_guest_req structure to eliminate the need to pass a long list of parameters. This structure will be used to call the SNP Guest message request API, simplifying the function arguments. Update the snp_issue_guest_request() prototype to include the new guest request structure. Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20241009092850.197575-5-nikunj@amd.com
2024-10-16x86/sev: Cache the secrets page addressNikunj A Dadhania
Instead of calling get_secrets_page(), which parses the CC blob every time to get the secrets page physical address (secrets_pa), save the secrets page physical address during snp_init() from the CC blob. Since get_secrets_page() is no longer used, remove the function. Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20241009092850.197575-4-nikunj@amd.com
2024-10-16x86/sev: Handle failures from snp_init()Nikunj A Dadhania
Address the ignored failures from snp_init() in sme_enable(). Add error handling for scenarios where snp_init() fails to retrieve the SEV-SNP CC blob or encounters issues while parsing the CC blob. Ensure that SNP guests will error out early, preventing delayed error reporting or undefined behavior. Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Link: https://lore.kernel.org/r/20241009092850.197575-3-nikunj@amd.com
2024-10-16virt: sev-guest: Use AES GCM crypto libraryNikunj A Dadhania
The sev-guest driver encryption code uses the crypto API for SNP guest messaging with the AMD Security processor. In order to enable secure TSC, SEV-SNP guests need to send such a TSC_INFO message before the APs are booted. Details from the TSC_INFO response will then be used to program the VMSA before the APs are brought up. However, the crypto API is not available this early in the boot process. In preparation for moving the encryption code out of sev-guest to support secure TSC and to ease review, switch to using the AES GCM library implementation instead. Drop __enc_payload() and dec_payload() helpers as both are small and can be moved to the respective callers. Signed-off-by: Nikunj A Dadhania <nikunj@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Peter Gonda <pgonda@google.com> Link: https://lore.kernel.org/r/20241009092850.197575-2-nikunj@amd.com
2024-10-16arm64: head: Drop SWAPPER_TABLE_SHIFTGavin Shan
There is no users of SWAPPER_TABLE_SHIFT after commit 84b04d3e6bdb ("arm64: kernel: Create initial ID map from C code"). Just drop it. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20241014030341.995806-1-gshan@redhat.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64/sysreg: Update ID_AA64MMFR1_EL1 to DDI0601 2024-09Mark Brown
ID_AA64MMFR1_EL1 has been updated by the architecture to enumerate several new architectural features since the last time sysreg was updated, sync with the definnition in DD0601 2024-09 to include two new versions of each of ETS and HAFDBS. Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241011-arm64-aa64mmfr1-2024-09-v1-1-61935a085010@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64: dts: qcom: x1e80100: rename vph-pwr regulator nodesJohan Hovold
Rename the x1e80100 vph-pwr regulator nodes to use "regulator" as a prefix for consistency with the other fixed regulators. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241015122601.16127-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-16arm64: cpufeature: add POE to cpucap_is_possible()Joey Gouly
Since de66cb37ab6 ("arm64: Add cpucap_is_possible()"), alternative_has_cap_unlikely() includes the IS_ENABLED() check. Add CONFIG_ARM64_POE to cpucap_is_possible() to avoid the explicit check. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20241008140121.2774348-1-joey.gouly@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16riscv: defconfig: enable gpio support for TH1520Drew Fustini
Enable gpio-dwapb driver which is used by TH1520-based boards like the BeagleV Ahead and the Sipeed LicheePi 4A. Signed-off-by: Drew Fustini <drew@pdp7.com> Link: https://lore.kernel.org/r/20241014205315.1349391-1-drew@pdp7.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-10-16hugetlb: arm64: add mte supportYang Shi
Enable MTE support for hugetlb. The MTE page flags will be set on the folio only. When copying hugetlb folio (for example, CoW), the tags for all subpages will be copied when copying the first subpage. When freeing hugetlb folio, the MTE flags will be cleared. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Yang Shi <yang@os.amperecomputing.com> Link: https://lore.kernel.org/r/20241001225220.271178-1-yang@os.amperecomputing.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64/mm: Change pgattr_change_is_safe() arguments as pteval_tAnshuman Khandual
pgattr_change_is_safe() processes two distinct page table entries that just happen to be 64 bits for all levels. This changes both arguments to reflect the actual data type being processed in the function. This change is important when moving to FEAT_D128 based 128 bit page tables because it makes it simple to change the entry size in one place. Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Ryan Roberts <ryan.roberts@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20241001045804.1119881-1-anshuman.khandual@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64: optimize flush tlb kernel rangeKefeng Wang
Currently the kernel TLBs is flushed page by page if the target VA range is less than MAX_DVM_OPS * PAGE_SIZE, otherwise we'll brutally issue a TLBI ALL. But we could optimize it when CPU supports TLB range operations, convert to use __flush_tlb_range_op() like other tlb range flush to improve performance. Co-developed-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20240923131351.713304-3-wangkefeng.wang@huawei.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64: tlbflush: add __flush_tlb_range_limit_excess()Kefeng Wang
The __flush_tlb_range_limit_excess() helper will be used when flush tlb kernel range soon. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20240923131351.713304-2-wangkefeng.wang@huawei.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2024-10-16arm64: dts: mediatek: mt8188: Add eDP and DP TX nodesFei Shao
Add edp-tx and dp-tx nodes for the Embedded DisplayPort (eDP) and DisplayPort ports to connect to DP-INTF ports and panels, and add the efuse cell for the DP calibration data. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-10-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add DP-INTF nodesFei Shao
Add the primary and secondary dp-intf nodes. These DP-INTF hardware IPs are the sink of the vdosys0 and vdosys1 display pipelines for the internal and external displays, respectively. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-9-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add display nodes for vdosys1Fei Shao
Add the vdosys1 display nodes to support the external display pipeline. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-8-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add display nodes for vdosys0Fei Shao
Add the vdosys0 display nodes to support the internal display pipeline. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-7-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add JPEG decoder and encoder nodesFei Shao
Add JPEG encoder and decoder nodes for hardware-accelerated JPEG decoding and encoding support. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-6-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add video decoder and encoder nodesFei Shao
Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-5-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add MIPI DSI nodesFei Shao
Add two MIPI DSI nodes and the associated PHY nodes to support DSI panels. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-4-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add PCIe nodesFei Shao
Add PCIe node and the associated PHY node. Individual board device tree should enable the nodes as needed. Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-3-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Assign GCE aliasesFei Shao
Create and assign aliases for the MediaTek GCE mailboxes. Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241014111053.2294519-2-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8390-genio-700-evk: add keys and USB HUBMacpaul Lin
1. Add i2c, mmc to aliases. 4. Add PMIC_KEY setting. 5. Add USB HUB TUSB8020 to xhci1. 6. Re-order spi2 node. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://lore.kernel.org/r/20241007090244.1731-2-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8390-genio-700-evk: update regulator namesMacpaul Lin
Update regulator names to match schematics, replacing generic terms. 1. Add system wide 'reg_vsys' node for 4.2V power rail. 2. Add 'reg_vsys' node as 'vin-supply' for the following nodes - common_fixed_5v, edp_panel_fixed_3v3, gpio_fixed_3v3, sdio_fixed_3v3, touch0_fixed_3v3, usb_hub_fixed_3v3, usb_p0_vbus, and usb_p1_vbus. 3. Update regulator names according to the stable output name on schematics. - vdd_5v, vedp_3v3, ext_3v3, vio18_conn, wifi_3v3, vio33_tp1, vhub_3v3, vbus_p0, vbus_p1. - vcn18_pmu, vcn33_2_pmu, dvdd_proc_l, dvdd_core, vpa_pmu, dvdd_adsp, va12_abb2_pmu, vsim1_pmu, vufs18_pmu. 4. Remove usb_hub_reset_1v8. Use 'hub' node to probe USB HUB in subsequent patches. Suggested-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241007090244.1731-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8390-genio-700-evk: enable pcieMacpaul Lin
Enable PCIE, PCIEPHY and related Pinctrls for mt8390-genio-700-evk board. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241007100749.6657-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mt8183: kukui: Fix the address of eeprom at i2c4Hsin-Te Yuan
The address of eeprom should be 50. Fixes: ff33d889567e ("arm64: dts: mt8183: Add kukui kodama board") Fixes: d1eaf77f2c66 ("arm64: dts: mt8183: Add kukui kakadu board") Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240909-eeprom-v1-2-1ed2bc5064f4@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mt8183: krane: Fix the address of eeprom at i2c4Hsin-Te Yuan
The address of eeprom should be 50. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20240909-eeprom-v1-1-1ed2bc5064f4@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt7988: add efuse blockRafał Miłecki
MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration data. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt7988: add UART controllersRafał Miłecki
MT7988 has three on-SoC UART controllers that support M16C450 and M16550A modes. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mt8183: Add encoder nodeHsin-Te Yuan
Add encoder node. Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Link: https://lore.kernel.org/r/20240911-venc-v2-1-5566c07756fd@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8395-genio-1200-evk: Enable GPUPablo Sun
Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator supply settingsi to gpu and mfg1, and enable the GPU node. In addition, set the GPU related regulator voltage range: 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V), based on Table 5-3 of MT8395 Application Processor Datasheet. The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input. Note that the minimum voltage in SoC eFuse data, which is read by MTK-SVS to adjust the regulator voltage, does not go below the recommended operating voltage in the datasheet. 2. Set the input voltage of DVDD_SRAM_GPU, supplied by mt6359_vsram_others_ldo_reg, to 0.75V, the recommended typical operating voltage in MT8395 Application Processor Datasheet. This patch is tested by enabling CONFIG_DRM_PANFROST and on Genio 1200 EVK it probed with following dmesg: ``` panfrost 13000000.gpu: clock rate = 700000092 panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0 panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000001,80000400 panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x301 MMU:0x00002830 AS:0xff JS:0x7 panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1 [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0 ``` Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20240912070624.25540-1-pablo.sun@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add socinfo nodesFei Shao
Add two socinfo efuse data nodes for the SoC information probing on MT8188. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20240911143429.850071-9-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16arm64: dts: mediatek: mt8188: Add audio supportFei Shao
Add following nodes to support audio enablement on MT8188 SoC: - sound card - audio controller (AFE) - audio DSP and its associated mailboxes Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20240911143429.850071-8-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-10-16s390/pci: Align prototypes of zpci IO memcpy functionsJulian Vetter
The generic memcpy_{from,to}io and memset_io functions have a different prototype than the zpci_memcpy_{from,to}io and zpci_memset_io functions. But in driver code zpci functions are used as IO memcpy directly. So, align their prototypes. Signed-off-by: Julian Vetter <jvetter@kalrayinc.com> Link: https://lore.kernel.org/r/20241010130100.710005-2-jvetter@kalrayinc.com Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2024-10-16s390: Update defconfigsHeiko Carstens
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2024-10-16s390: Initialize psw mask in perf_arch_fetch_caller_regs()Heiko Carstens
Also initialize regs->psw.mask in perf_arch_fetch_caller_regs(). This way user_mode(regs) will return false, like it should. It looks like all current users initialize regs to zero, so that this doesn't fix a bug currently. However it is better to not rely on callers to do this. Fixes: 914d52e46490 ("s390: implement perf_arch_fetch_caller_regs") Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2024-10-16ARM: dts: nxp: imx6ull: add dma support for uart8Sean Nyekjaer
Add dma support on uart8. Signed-off-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-10-16ARM: dts: nxp: imx6ul: add dma support for all uartsSean Nyekjaer
Add dma support on uart1, uart2, uart3, uart4, uart5, uart6 and uart7. Signed-off-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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