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2025-02-03ARM: zynq: Fix fpga region DT nodes nameMichal Simek
fpga-full is not aligned with the latest dt-schema. Generic name fpga-region should be used. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0fcce9f0fa4fc2e170a7c5374d0b4063fa0bbd71.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Rename i2c?-gpio to i2c?-gpio-grpMichal Simek
Anything ending with gpio/gpios is taken as gpio phande/description which is reported as the issue coming from gpio-consumer.yaml schema. That's why rename the gpio suffix to gpio-grp to avoid name collision. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/43b2f451bfd2ebce70f3ac6442586838d3e21951.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Define rtc alias on zc702/zc706Michal Simek
Define rtc alias on zc702/zc706 boards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9ee86a22d15fb127b8b31cf1ab6059ffb05ad55b.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706Michal Simek
EEPROM stores identification information about board like a board name, revision, serial number and ethernet MAC address. U-Boot is capable to read nvmemX aliases and read/display provided information when nvmem alias link is described. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c4a28874455a8747638551cf09ba31aa803b8b09.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Define u-boot bootscrip addr via DTMichal Simek
Define bootscript address in RAM via DT property. Adding default value to common DTSI. Platform DT description can remove this property or rewrite it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9252bb464c5c82fda6018ea450c6f453a5d8412c.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Wire smcc with nand/nor memories on zc770 platformMichal Simek
Describe nor child flash node under smcc and enable it for xm012 extension card. And also describe nand flash memory for xm011 card. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/12e697975a1d026e811c2f63aa8bbbd0b9ff4f70.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Mark boot-phase-specific device nodesMichal Simek
Tag boot specific device nodes which are required for booting. In our case this is sync up with U-Boot project where all these IPs are already tagged and tested. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f25387e0123ee81f7d8246add3c6ec063f3cfa78.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: DT: List OCM memory for all platformsMichal Simek
Move OCM description from zc702 to all zynq boards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/68da82d3d0733e33672562487a9df4a9374d8e1a.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Remove deprecated device_type propertyMichal Simek
Based on DT specification device_type property is deprecated and should be used only for cpu and memory nodes. That's why remove other usage. In this case ethernet phy. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/77152dc14271a2340f63e6d407f36293ed656d49.1733920873.git.michal.simek@amd.com
2025-02-03ARM: zynq: Replace 'io-standard' with 'power-source' propertySai Krishna Potthuri
Replace 'io-standard' property with 'power-source' property in all zynq dts files to be in sync with Zynq Pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/cf45ed95fe0be083446d5aaf5f946f38acba7728.1733920873.git.michal.simek@amd.com
2025-02-03m68k: sun3: Fix DEBUG_MMU_EMU buildGeert Uytterhoeven
With DEBUG_MMU_EMU enabled: arch/m68k/sun3/mmu_emu.c: In function ‘mmu_emu_handle_fault’: arch/m68k/sun3/mmu_emu.c:420:38: error: implicit declaration of function ‘get_fs’; did you mean ‘sget_fc’? [-Werror=implicit-function-declaration] 420 | pr_info("seg:%ld crp:%p ->", get_fs().seg, crp); | ^~~~~~ [...] arch/m68k/sun3/mmu_emu.c:420:46: error: request for member ‘seg’ in something not a structure or union 420 | pr_info("seg:%ld crp:%p ->", get_fs().seg, crp); | ^ Fix this by reintroducing and using a helper to retrieve the current value of the DFC register. While at it, replace "%p" by "%px", as there is no point in printing obfuscated pointers during debugging. Fixes: 9fde0348640252c7 ("m68k: Remove set_fs()") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/b1d12a1d24b4aea9f98d905383ba932b2dc382e6.1737387419.git.geert@linux-m68k.org
2025-02-03m68k: sun3: Use str_read_write() helper in mmu_emu_handle_fault()Thorsten Blum
Remove hard-coded strings by using the str_read_write() helper. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: https://lore.kernel.org/20250117120605.126941-2-thorsten.blum@linux.dev Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2025-02-03ARM: s3c: Do not include <linux/fb.h>Thomas Zimmermann
These ARM architecture's source files do not require <linux/fb.h>. Remove the include statements. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250203102818.56747-3-tzimmermann@suse.de Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-03ARM: dts: stm32: lxa-fairytux2: add Linux Automation GmbH FairyTux 2Leonard Göhrs
The Linux Automation GmbH FairyTux2 is a small Linux device based on an Octavo Systems OSD32MP153c SiP, that occupies just two slots on a DIN rail. The device contains an eMMC for storage, a gigabit Ethernet connection, a CAN bus and a RS485 transceiver. Add support for the lxa-fairytux2 generation 1 and 2 boards based on the STM32MP153c. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-02-03perf/amd/ibs: Ceil sample_period to min_periodRavi Bangoria
The sample_period needs to be recalibrated after every sample to match the desired sampling freq for a 'freq mode event'. Since the next sample_period is calculated by generic kernel, PMU specific constraints are not (explicitly) reckoned. The sample_period value is programmed in a MaxCnt field of IBS PMUs, and the MaxCnt field has following constraints: 1) MaxCnt must be multiple of 0x10. Kernel keeps track of residual / over-counted period into period_left, which should take care of this constraint by programming MaxCnt with (sample_period & ~0xF) and adding remaining period into the next sample. 2) MaxCnt must be >= 0x10 for IBS Fetch PMU and >= 0x90 for IBS Op PMU. Currently, IBS PMU driver allows sample_period below min_period, which is an undefined HW behavior. Reset sample_period to min_period whenever it's less than that. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20250115054438.1021-9-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Add ->check_period() callbackRavi Bangoria
IBS Fetch and IBS Op PMUs have constraints on sample period. The sample period is verified at the time of opening an event but not at the ioctl() interface. Hence, a user can open an event with valid period but change it later with ioctl(). Add a ->check_period() callback to verify the period provided at ioctl() is also valid. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-8-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Add PMU specific minimum periodRavi Bangoria
0x10 is the minimum sample period for IBS Fetch and 0x90 for IBS Op. Current IBS PMU driver uses 0x10 for both the PMUs, which is incorrect. Fix it by adding PMU specific minimum period values in struct perf_ibs. Also, bail out opening a 'sample period mode' event if the user requested sample period is less than PMU supported minimum value. For a 'freq mode' event, start calibrating sample period from PMU specific minimum period. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-7-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Don't allow freq mode event creation through ->config interfaceRavi Bangoria
Most perf_event_attr->config bits directly maps to IBS_{FETCH|OP}_CTL MSR. Since the sample period is programmed in these control registers, IBS PMU driver allows opening an IBS event by setting sample period value directly in perf_event_attr->config instead of using explicit perf_event_attr->sample_period interface. However, this logic is not applicable for freq mode events since the semantics of control register fields are applicable only to fixed sample period whereas the freq mode event adjusts sample period after each and every sample. Currently, IBS driver (unintentionally) allows creating freq mode event via ->config interface, which is semantically wrong as well as detrimental because it can be misused to bypass perf_event_max_sample_rate checks. Don't allow freq mode event creation through perf_event_attr->config interface. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-6-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCntRavi Bangoria
IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Fix ->config to sample period calculation for OP PMURavi Bangoria
Instead of using standard perf_event_attr->freq=0 and ->sample_period fields, IBS event in 'sample period mode' can also be opened by setting period value directly in perf_event_attr->config in a MaxCnt bit-field format. IBS OP MaxCnt bits are defined as: (high bits) IbsOpCtl[26:20] = IbsOpMaxCnt[26:20] (low bits) IbsOpCtl[15:0] = IbsOpMaxCnt[19:4] Perf event sample period can be derived from MaxCnt bits as: sample_period = (high bits) | ((low_bits) << 4); However, current code just masks MaxCnt bits and shifts all of them, including high bits, which is incorrect. Fix it. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-4-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Remove pointless sample period checkRavi Bangoria
Valid perf event sample period value for IBS PMUs (Fetch and Op both) is limited to multiple of 0x10. perf_ibs_init() has this check: if (!event->attr.sample_freq && hwc->sample_period & 0x0f) return -EINVAL; But it's broken since hwc->sample_period will always be 0 when event->attr.sample_freq is 0 (irrespective of event->attr.freq value.) One option to fix this is to change the condition: - if (!event->attr.sample_freq && hwc->sample_period & 0x0f) + if (!event->attr.freq && hwc->sample_period & 0x0f) However, that will break all userspace tools which have been using IBS event with sample_period not multiple of 0x10. Another option is to remove the condition altogether and mask lower nibble _silently_, same as what current code is inadvertently doing. I'm preferring this approach as it keeps the existing behavior. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-3-ravi.bangoria@amd.com
2025-02-03perf/amd/ibs: Remove IBS_{FETCH|OP}_CONFIG_MASK macrosRavi Bangoria
Definition of these macros are very simple and they are used at only one place. Get rid of unnecessary redirection. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20250115054438.1021-2-ravi.bangoria@amd.com
2025-02-03x86/mm: Fix flush_tlb_range() when used for zapping normal PMDsJann Horn
On the following path, flush_tlb_range() can be used for zapping normal PMD entries (PMD entries that point to page tables) together with the PTE entries in the pointed-to page table: collapse_pte_mapped_thp pmdp_collapse_flush flush_tlb_range The arm64 version of flush_tlb_range() has a comment describing that it can be used for page table removal, and does not use any last-level invalidation optimizations. Fix the X86 version by making it behave the same way. Currently, X86 only uses this information for the following two purposes, which I think means the issue doesn't have much impact: - In native_flush_tlb_multi() for checking if lazy TLB CPUs need to be IPI'd to avoid issues with speculative page table walks. - In Hyper-V TLB paravirtualization, again for lazy TLB stuff. The patch "x86/mm: only invalidate final translations with INVLPGB" which is currently under review (see <https://lore.kernel.org/all/20241230175550.4046587-13-riel@surriel.com/>) would probably be making the impact of this a lot worse. Fixes: 016c4d92cd16 ("x86/mm/tlb: Add freed_tables argument to flush_tlb_mm_range") Signed-off-by: Jann Horn <jannh@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20250103-x86-collapse-flush-fix-v1-1-3c521856cfa6@google.com
2025-02-03x86: re-enable EXECMEM_ROX supportMike Rapoport (Microsoft)
after rework of execmem ROX caches Signed-off-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250126074733.1384926-10-rppt@kernel.org
2025-02-03Revert "x86/module: prepare module loading for ROX allocations of text"Mike Rapoport (Microsoft)
The module code does not create a writable copy of the executable memory anymore so there is no need to handle it in module relocation and alternatives patching. This reverts commit 9bfc4824fd4836c16bb44f922bfaffba5da3e4f3. Signed-off-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250126074733.1384926-8-rppt@kernel.org
2025-02-03x86/mm/pat: restore large ROX pages after fragmentationKirill A. Shutemov
Change of attributes of the pages may lead to fragmentation of direct mapping over time and performance degradation when these pages contain executable code. With current code it's one way road: kernel tries to avoid splitting large pages, but it doesn't restore them back even if page attributes got compatible again. Any change to the mapping may potentially allow to restore large page. Add a hook to cpa_flush() path that will check if the pages in the range that were just touched can be mapped at PMD level. If the collapse at the PMD level succeeded, also attempt to collapse PUD level. The collapse logic runs only when a set_memory_ method explicitly sets CPA_COLLAPSE flag, for now this is only enabled in set_memory_rox(). CPUs don't like[1] to have to have TLB entries of different size for the same memory, but looks like it's okay as long as these entries have matching attributes[2]. Therefore it's critical to flush TLB before any following changes to the mapping. Note that we already allow for multiple TLB entries of different sizes for the same memory now in split_large_page() path. It's not a new situation. set_memory_4k() provides a way to use 4k pages on purpose. Kernel must not remap such pages as large. Re-use one of software PTE bits to indicate such pages. [1] See Erratum 383 of AMD Family 10h Processors [2] https://lore.kernel.org/linux-mm/1da1b025-cabc-6f04-bde5-e50830d1ecf0@amd.com/ [rppt@kernel.org: * s/restore/collapse/ * update formatting per peterz * use 'struct ptdesc' instead of 'struct page' for list of page tables to be freed * try to collapse PMD first and if it succeeds move on to PUD as peterz suggested * flush TLB twice: for changes done in the original CPA call and after collapsing of large pages * update commit message ] Signed-off-by: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Co-developed-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250126074733.1384926-4-rppt@kernel.org
2025-02-03x86/mm/pat: drop duplicate variable in cpa_flush()Mike Rapoport (Microsoft)
There is a 'struct cpa_data *data' parameter in cpa_flush() that is assigned to a local 'struct cpa_data *cpa' variable. Rename the parameter from 'data' to 'cpa' and drop declaration of the local 'cpa' variable. Signed-off-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250126074733.1384926-3-rppt@kernel.org
2025-02-03x86/mm/pat: cpa-test: fix length for CPA_ARRAY testMike Rapoport (Microsoft)
The CPA_ARRAY test always uses len[1] as numpages argument to change_page_attr_set() although the addresses array is different each iteration of the test loop. Replace len[1] with len[i] to have numpages matching the addresses array. Fixes: ecc729f1f471 ("x86/mm/cpa: Add ARRAY and PAGES_ARRAY selftests") Signed-off-by: "Mike Rapoport (Microsoft)" <rppt@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250126074733.1384926-2-rppt@kernel.org
2025-02-03microblaze: Use of_property_present() for non-boolean propertiesRob Herring (Arm)
The use of of_property_read_bool() for non-boolean properties is deprecated in favor of of_property_present() when testing for property presence. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241231161424.214934-1-robh@kernel.org Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-02-03ARM: shmobile: rcar-gen2: Remove CMA reservation codeGeert Uytterhoeven
If CONFIG_HIGHMEM=y, two reserved blocks are allocated on R-Car Gen2: cma: Reserved 256 MiB at 0x70000000 on node -1 cma: Reserved 64 MiB at 0x6c000000 on node -1 The first block is reserved by the family-specific rcar_gen2_reserve(), the second by the common arm_memblock_init() (shmobile_defconfig sets CONFIG_CMA_SIZE_MBYTES=64). As both blocks are reserved (eventually) using dma_contiguous_reserve_area(), they both have the same name ("reserved"). Hence if CONFIG_CMA_SYSFS=y: sysfs: cannot create duplicate filename '/kernel/mm/cma/reserved' ... cma_sysfs_init from do_one_initcall+0x84/0x178 ... kobject: kobject_add_internal failed for reserved with -EEXIST, don't try to register things with the same name in the same directory. This causes cma_sysfs_init() to fail completely, and not to create /sys/kernel/mm/cma/ at all. Fix this by dropping the R-Car Gen2-specific reservation. Compared to when it was introduced, now there exist more flexible mechanisms to control the size of memory reserved for CMA. Users can reserve more memory by increasing CONFIG_CMA_SIZE_MBYTES, passing the cma=<N> kernel command line parameter, or adding a reserved-memory/linux,cma node to DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/3d38f4fec20c4af46e4570012de7017eee9a39e9.1736249109.git.geert+renesas@glider.be
2025-02-03ARM: shmobile: defconfig: Supplement DTB with ATAG informationNiklas Söderlund
Enable CONFIG_ARM_ATAG_DTB_COMPAT to allow U-Boot to override kernel command line from DTB using the bootargs argument. This is needed at least on R-Car H1 Marzen to control the command line from U-Boot. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250116153204.615736-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-02-03arm64: dts: rockchip: Fix lcdpwr_en pin for Cool Pi GenBookAndy Yan
According to the schematic, the lcdpwr_en pin is GPIO0_C4, not GPIO1_C4. Fixes: 4a8c1161b843 ("arm64: dts: rockchip: Add support for rk3588 based Cool Pi CM5 GenBook") Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250113104825.2390427-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: fix fixed-regulator renames on rk3399-gru devicesHeiko Stuebner
rk3399-gru chromebooks have a regulator chains where one named regulator supplies multiple regulators pp900-usb pp900_pcie that supply the named peripherals. The dtsi used somewhat creative structure to describe that in creating the base node 3 times with different phandles and describing the EC dependency in a comment. This didn't register in the recent regulator-node renaming, as the additional nodes were empty, so adapt the missing node names for now. Fixes: 5c96e6330197 ("arm64: dts: rockchip: adapt regulator nodenames to preferred form") Tested-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250116143631.3650469-1-heiko@sntech.de
2025-02-03arm64: dts: rockchip: Disable DMA for uart5 on px30-ringneckLukasz Czechowski
UART controllers without flow control seem to behave unstable in case DMA is enabled. The issues were indicated in the message: https://lore.kernel.org/linux-arm-kernel/CAMdYzYpXtMocCtCpZLU_xuWmOp2Ja_v0Aj0e6YFNRA-yV7u14g@mail.gmail.com/ In case of PX30-uQ7 Ringneck SoM, it was noticed that after couple of hours of UART communication, the CPU stall was occurring, leading to the system becoming unresponsive. After disabling the DMA, extensive UART communication tests for up to two weeks were performed, and no issues were further observed. The flow control pins for uart5 are not available on PX30-uQ7 Ringneck, as configured by pinctrl-0, so the DMA nodes were removed on SoM dtsi. Cc: stable@vger.kernel.org Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250121125604.3115235-3-lukasz.czechowski@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoMLukasz Czechowski
In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for uart5 cannot be used for the UART CTS/RTS, because they are already allocated for different purposes. CTS pin is routed to SUS_S3# signal, while RTS pin is used internally and is not available on Q7 connector. Move definition of the pinctrl-0 property from px30-ringneck-haikou.dts to px30-ringneck.dtsi. This commit is a dependency to next commit in the patch series, that disables DMA for uart5. Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: change eth phy mode to rgmii-id for orangepi r1 plus ltsTianling Shen
In general the delay should be added by the PHY instead of the MAC, and this improves network stability on some boards which seem to need different delay. Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS") Cc: stable@vger.kernel.org # 6.6+ Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20250119091154.1110762-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Fix broken tsadc pinctrl names for rk3588Alexander Shiyan
The tsadc driver does not handle pinctrl "gpio" and "otpout". Let's use the correct pinctrl names "default" and "sleep". Additionally, Alexey Charkov's testing [1] has established that it is necessary for pinctrl state to reference the &tsadc_shut_org configuration rather than &tsadc_shut for the driver to function correctly. [1] https://lkml.org/lkml/2025/1/24/966 Fixes: 32641b8ab1a5 ("arm64: dts: rockchip: add rk3588 thermal sensor") Cc: stable@vger.kernel.org Reviewed-by: Dragan Simic <dsimic@manjaro.org> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Link: https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsiDragan Simic
The preferred way to denote hardware with non-coherent DMA is to use the "dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS levels, [1] instead of relying on the compatibles to handle hardware errata, in this case the Rockchip 3588001 errata. [2] Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi, which also goes along with adding initial support for the Rockchip RK3582 SoC variant, with its separate compatible. [2][3] [1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml [2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/ [3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/ Cc: Marc Zyngier <maz@kernel.org> Cc: FUKAUMI Naoki <naoki@radxa.com> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Describe why is HWRNG disabled in RK356x base dtsiDragan Simic
Despite the presence of the hardware random number generator (HWRNG) in the different Rockchip RK356x SoC variants, it remains disabled for the RK3566 SoC because testing showed [1] that it produces unacceptably low quality of random data, for some yet unknown reason. The HWRNG is enabled for the RK3568 SoC, on which the testing showed good quality of the generated random data. To avoid possible confusion in the future, [2] let's have this described briefly in the RK356x base SoC dtsi. [1] https://lore.kernel.org/linux-rockchip/cover.1720969799.git.daniel@makrotopia.org/T/#u [2] https://lore.kernel.org/linux-rockchip/20241201234613.52322-1-pbrobinson@gmail.com/T/#u Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/6b272e2f8f916c04b05db50df621659a5a7f29ab.1733149874.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Enable HDMI on armsom-sige7Jianfeng Liu
Add the necessary DT changes to enable HDMI on ArmSoM Sige7. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250115023327.2881820-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5CAlexey Charkov
Add the necessary cooling map to enable the kernel's thermal subsystem to manage the fan speed automatically depending on the overall SoC package temperature on Radxa Rock 5C Signed-off-by: Alexey Charkov <alchark@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-2-5fb8446c981b@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Add finer-grained PWM states for the fan on Rock 5CAlexey Charkov
Radxa Heatsink 6540B, which is the official cooling accessory for the Rock 5C board, includes a small 5V fan, which in my testing spins up reliably at a PWM setting of 24 (out of 255). It is also quite loud at the current minimum setting of 64, and noticeably less so at 24. Introduce two intermediate PWM states at the lower end of the fan's operating range to enable better balance between noise and cooling. Note further that, in my testing, having the fan run at 44 is enough to keep the system from thermal throttling with sustained 100% load on its 8 CPU cores (in 22C ambient temperature and no case) Signed-off-by: Alexey Charkov <alchark@gmail.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-1-5fb8446c981b@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: Enable USB OTG for Radxa ROCK Pi EFUKAUMI Naoki
The Radxa ROCK Pi E has USB D+/D- signals on the 40-pin header[1]. Enable it for use as an OTG port. [1] https://docs.radxa.com/en/rockpi/rockpie/hardware/gpio Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20250129064004.162136-1-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03arm64: dts: rockchip: add support for sound output over HDMI on RK3399 Puma ↵Quentin Schulz
Haikou The Haikou carrierboard exposes an HDMI connector and audio can also be output, therefore let's enable it on RK3399 Puma. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250130-rk3399-hdmi-audio-v1-1-406244333111@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-03ARM: dts: ti: davinci: Align GPIO hog name with bindingsKrzysztof Kozlowski
Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warnings like: da850-lego-ev3.dtb: batt_volt_en: $nodename:0: 'batt_volt_en' does not match '^.+-hog(-[0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/20250116090030.87452-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-02-03arm64: dts: imx8mp-skov-reva: Use hardware signal for SD card VSELECTFrieder Schrempf
The USDHC controller is able to control the IO voltage of the SD card. There is no reason to use a GPIO to control it. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://patch.msgid.link/20241218152842.97483-3-frieder@fris.de Signed-off-by: Mark Brown <broonie@kernel.org>
2025-02-02Merge tag 'sh-for-v6.14-tag1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux Pull sh updates from John Paul Adrian Glaubitz: "Fixes and improvements for sh: - replace seq_printf() with the more efficient seq_put_decimal_ull_width() to increase performance when stress reading /proc/interrupts (David Wang) - migrate sh to the generic rule for built-in DTB to help avoid race conditions during parallel builds which can occur because Kbuild decends into arch/*/boot/dts twice (Masahiro Yamada) - replace select with imply in the board Kconfig for enabling hardware with complex dependencies. This addresses warnings which were reported by the kernel test robot (Geert Uytterhoeven)" * tag 'sh-for-v6.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux: sh: boards: Use imply to enable hardware with complex dependencies sh: Migrate to the generic rule for built-in DTB sh: irq: Use seq_put_decimal_ull_width() for decimal values
2025-02-01Merge tag 'mips_6.14_1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fix from Thomas Bogendoerfer: "Revert commit breaking sysv ipc for o32 ABI" * tag 'mips_6.14_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: Revert "mips: fix shmctl/semctl/msgctl syscall for o32"
2025-02-01Merge tag 'mm-hotfixes-stable-2025-02-01-03-56' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull misc fixes from Andrew Morton: "21 hotfixes. 8 are cc:stable and the remainder address post-6.13 issues. 13 are for MM and 8 are for non-MM. All are singletons, please see the changelogs for details" * tag 'mm-hotfixes-stable-2025-02-01-03-56' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: (21 commits) MAINTAINERS: include linux-mm for xarray maintenance revert "xarray: port tests to kunit" MAINTAINERS: add lib/test_xarray.c mailmap, MAINTAINERS, docs: update Carlos's email address mm/hugetlb: fix hugepage allocation for interleaved memory nodes mm: gup: fix infinite loop within __get_longterm_locked mm, swap: fix reclaim offset calculation error during allocation .mailmap: update email address for Christopher Obbard kfence: skip __GFP_THISNODE allocations on NUMA systems nilfs2: fix possible int overflows in nilfs_fiemap() mm: compaction: use the proper flag to determine watermarks kernel: be more careful about dup_mmap() failures and uprobe registering mm/fake-numa: handle cases with no SRAT info mm: kmemleak: fix upper boundary check for physical address objects mailmap: add an entry for Hamza Mahfooz MAINTAINERS: mailmap: update Yosry Ahmed's email address scripts/gdb: fix aarch64 userspace detection in get_current_task mm/vmscan: accumulate nr_demoted for accurate demotion statistics ocfs2: fix incorrect CPU endianness conversion causing mount failure mm/zsmalloc: add __maybe_unused attribute for is_first_zpdesc() ...
2025-02-01revert "xarray: port tests to kunit"Andrew Morton
Revert c7bb5cf9fc4e ("xarray: port tests to kunit"). It broke the build when compiing the xarray userspace test harness code. Reported-by: Sidhartha Kumar <sidhartha.kumar@oracle.com> Closes: https://lkml.kernel.org/r/07cf896e-adf8-414f-a629-a808fc26014a@oracle.com Cc: David Gow <davidgow@google.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Tamir Duberstein <tamird@gmail.com> Cc: "Liam R. Howlett" <Liam.Howlett@oracle.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-09 12:57:52 +0000