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2022-05-18ARM: 9197/1: spectre-bhb: fix loop8 sequence for Thumb2Ard Biesheuvel
In Thumb2, 'b . + 4' produces a branch instruction that uses a narrow encoding, and so it does not jump to the following instruction as expected. So use W(b) instead. Fixes: 6c7cb60bff7a ("ARM: fix Thumb2 regression with Spectre BHB") Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-05-18ARM: 9196/1: spectre-bhb: enable for Cortex-A15Ard Biesheuvel
The Spectre-BHB mitigations were inadvertently left disabled for Cortex-A15, due to the fact that cpu_v7_bugs_init() is not called in that case. So fix that. Fixes: b9baf5c8c5c3 ("ARM: Spectre-BHB workaround") Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-05-17ARM: dts: at91: sama7g5ek: add node for PDMC0Codrin Ciubotariu
SAMA7G5-EK has 4 PDM microphones connected to PDMC0. PDMC0 pinmux is in conflict with gmac1, gmac1 being enabled by default. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220307122202.2251639-6-codrin.ciubotariu@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-17ARM: dts: at91: sama7g5: add nodes for PDMCCodrin Ciubotariu
Microchip's SAMA7G5 embeds two PDMCs. The PDMCs can be used to connect 2x4 PDM microphones. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220307122202.2251639-5-codrin.ciubotariu@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-17ARM: dts: at91: Use the generic "rtc" node name for the rtt IPsSergiu Moga
As the DT specification recommends, the node names should be of a generic nature. Thus, the most appropriate generic node name for the at91 rtt IPs is the "rtc" node name. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220304161159.147784-3-sergiu.moga@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-17ARM: dts: at91: Add the required 'atmel, rtt-rtc-time-reg' propertySergiu Moga
Add the required 'atmel,rtt-rtc-time-reg' property to the "rtt" nodes of the board files that were missing it. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/all/20220304161159.147784-2-sergiu.moga@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-17ARM: at91: pm: Fix rand build errorYueHaibing
If ATMEL_PM is y but PM is n, build fails: arch/arm/mach-at91/pm.c:1435:13: error: redefinition of 'at91rm9200_pm_init' void __init at91rm9200_pm_init(void) ^~~~~~~~~~~~~~~~~~ In file included from arch/arm/mach-at91/pm.c:29:0: arch/arm/mach-at91/generic.h:19:27: note: previous definition of 'at91rm9200_pm_init' was here static inline void __init at91rm9200_pm_init(void) { } ^~~~~~~~~~~~~~~~~~ ATMEL_PM should not be enabled independently, it is only selected by Soc. Fixes: f2f5cf78a333 ("ARM: at91: pm: add support for sama5d2 secure suspend") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220517031606.11628-1-yuehaibing@huawei.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-17Merge branch irq/gic-v3-nmi-fixes-5.19 into irq/irqchip-nextMarc Zyngier
* irq/gic-v3-nmi-fixes-5.19: : . : GICv3 pseudo-NMI fixes from Mark Rutland: : : "These patches fix a couple of issues with the way GICv3 pseudo-NMIs are : handled: : : * The first patch adds a barrier we missed from NMI handling due to an : oversight. : : * The second patch refactors some logic around reads from ICC_IAR1_EL1 : and adds commentary to explain what's going on. : : * The third patch descends into madness, reworking gic_handle_irq() to : consistently manage ICC_PMR_EL1 + DAIF and avoid cases where these can : be left in an inconsistent state while softirqs are processed." : . irqchip/gic-v3: Fix priority mask handling irqchip/gic-v3: Refactor ISB + EOIR at ack time irqchip/gic-v3: Ensure pseudo-NMIs have an ISB between ack and handling Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-05-17irqchip: Add Kconfig symbols for sunxi driversSamuel Holland
Not all of these drivers are needed on every ARCH_SUNXI platform. In particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1, a RISC-V SoC which contains none of these irqchips. Introduce Kconfig symbols so we can select only the drivers actually used by a particular set of platforms. This also lets us move the irqchip driver dependencies to a more appropriate location. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220509034941.30704-1-samuel@sholland.org
2022-05-15irqchip/gic-v3: Refactor ISB + EOIR at ack timeMark Rutland
There are cases where a context synchronization event is necessary between an IRQ being raised and being handled, and there are races such that we cannot rely upon the exception entry being subsequent to the interrupt being raised. To fix this, we place an ISB between a read of IAR and the subsequent invocation of an IRQ handler. When EOI mode 1 is in use, we need to EOI an interrupt prior to invoking its handler, and we have a write to EOIR for this. As this write to EOIR requires an ISB, and this is provided by the gic_write_eoir() helper, we omit the usual ISB in this case, with the logic being: | if (static_branch_likely(&supports_deactivate_key)) | gic_write_eoir(irqnr); | else | isb(); This is somewhat opaque, and it would be a little clearer if there were an unconditional ISB, with only the write to EOIR being conditional, e.g. | if (static_branch_likely(&supports_deactivate_key)) | write_gicreg(irqnr, ICC_EOIR1_EL1); | | isb(); This patch rewrites the code that way, with this logic factored into a new helper function with comments explaining what the ISB is for, as were originally laid out in commit: 39a06b67c2c1256b ("irqchip/gic: Ensure we have an ISB between ack and ->handle_irq") Note that since then, we removed the IAR polling in commit: 342677d70ab92142 ("irqchip/gic-v3: Remove acknowledge loop") ... which removed one of the two race conditions. For consistency, other portions of the driver are made to manipulate EOIR using write_gicreg() and explcit ISBs, and the gic_write_eoir() helper function is removed. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220513133038.226182-3-mark.rutland@arm.com
2022-05-13arm: use fallback for random_get_entropy() instead of zeroJason A. Donenfeld
In the event that random_get_entropy() can't access a cycle counter or similar, falling back to returning 0 is really not the best we can do. Instead, at least calling random_get_entropy_fallback() would be preferable, because that always needs to return _something_, even falling back to jiffies eventually. It's not as though random_get_entropy_fallback() is super high precision or guaranteed to be entropic, but basically anything that's not zero all the time is better than returning zero all the time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-05-13Merge tag 'v5.18-next-dts32' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt Delete no longer needed properties of MediaTek Larbs for MT2701. * tag 'v5.18-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm: dts: mediatek: Get rid of mediatek, larb for MM nodes Link: https://lore.kernel.org/r/b4383f23-0adc-b9de-a1d9-abd1c2f82b27@gmail.com This concludes a cleanup that was started back in 2019, with an incompatible DT binding change. Kernels before 5.18 can no longer use the updated dtb from 5.19, and the drivers no longer parse the old properties, which breaks compatibility with older dtb files. Link: https://lore.kernel.org/lkml/1546318276-18993-2-git-send-email-yong.wu@mediatek.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'at91-dt-5.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 & LAN966 DT #1 for 5.19: - at91: DT compliance updates to gic and dataflash nodes - lan966: addition to many basic nodes for various peripherals - lan966: Kontron KSwitch D10: support for this new board and its network switch * tag 'at91-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: kswitch-d10: enable networking ARM: dts: lan966x: add switch node ARM: dts: lan966x: add serdes node ARM: dts: lan966x: add reset switch reset node ARM: dts: lan966x: add MIIM nodes ARM: dts: lan966x: add hwmon node ARM: dts: lan966x: add basic Kontron KSwitch D10 support ARM: dts: lan966x: add flexcom I2C nodes ARM: dts: lan966x: add flexcom SPI nodes ARM: dts: lan966x: add all flexcom usart nodes ARM: dts: lan966x: add missing uart DMA channel ARM: dts: lan966x: add sgpio node ARM: dts: lan966x: swap dma channels for crypto node ARM: dts: lan966x: rename pinctrl nodes ARM: dts: at91: sama7g5: remove interrupt-parent from gic node ARM: dts: at91: use generic node name for dataflash Link: https://lore.kernel.org/r/20220513162338.87717-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'mm-hotfixes-stable-2022-05-11' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Pull misc fixes from Andrew Morton: "Seven MM fixes, three of which address issues added in the most recent merge window, four of which are cc:stable. Three non-MM fixes, none very serious" [ And yes, that's a real pull request from Andrew, not me creating a branch from emailed patches. Woo-hoo! ] * tag 'mm-hotfixes-stable-2022-05-11' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: MAINTAINERS: add a mailing list for DAMON development selftests: vm: Makefile: rename TARGETS to VMTARGETS mm/kfence: reset PG_slab and memcg_data before freeing __kfence_pool mailmap: add entry for martyna.szapar-mudlaw@intel.com arm[64]/memremap: don't abuse pfn_valid() to ensure presence of linear map procfs: prevent unprivileged processes accessing fdinfo dir mm: mremap: fix sign for EFAULT error return value mm/hwpoison: use pr_err() instead of dump_page() in get_any_page() mm/huge_memory: do not overkill when splitting huge_zero_page Revert "mm/memory-failure.c: skip huge_zero_page in memory_failure()"
2022-05-13Merge tag 'mvebu-arm-5.19-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/soc mvebu arm for 5.19 (part 1) Fix typos in comment on orion5x files * tag 'mvebu-arm-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: orion5x: fix typos in comments Link: https://lore.kernel.org/r/87o801r2ss.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'mvebu-dt-5.19-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt for 5.19 (part 1) Add the crypto module atsha204a node for the turis omnia (Armada 385 bases) * tag 'mvebu-dt-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dts: turris-omnia: Add atsha204a node Link: https://lore.kernel.org/r/87lev5r2rg.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13ARM: dts: kswitch-d10: enable networkingMichael Walle
Enable all the necessary network related nodes, wire the pinctrl configurations, add the PHYs and connect them to the corresponding network ports. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-14-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add switch nodeMichael Walle
Add the switch node and its 8 children ports. All are disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-13-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add serdes nodeMichael Walle
Add the SerDes node. On the LAN966x SoC these SerDes are used to connect network PHYs. By default, that node is disabled. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-12-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add reset switch reset nodeMichael Walle
Add the switch reset node which will later be used by the switch driver. The switch reset also resets the GPIO controller and the SGPIO controller, thus it also has to be connectected to these nodes. This way the reset will only issued once for the first device requesting the reset. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-11-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add MIIM nodesMichael Walle
Add the MDIO controller nodes. The integrated PHYs are connected to the second controller. This controller also takes care of the resets of the integrated PHYs, thus it has two memory regions. The first controller is routed to the external MDIO/MDC pins. By default, they are disabled. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add hwmon nodeMichael Walle
Add the monitoring node which covers the temperature sensor as well as the PWM controller and the FAN tacho input. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-9-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add basic Kontron KSwitch D10 supportMichael Walle
Add basic support for the Kontron KSwitch D10 MMT. It comes in two variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP cages and "8G" which features 6 Gigbabit copper ports (where two are 2.5G capable). For now the following is supported and working: - Kernel console - SFP cages - SPI - SGPIO - Watchdog Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> [claudiu.beznea: fixed conflict on Makefile] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-8-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add flexcom I2C nodesMichael Walle
Add all I2C nodes of the flexcom IP blocks. The driver supports FIFO, DMA or both combined. But the latter isn't working correctly. Thus, skip the fifo-size property for now. DMA is doing single byte reads in this case. Keep the nodes disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-7-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add flexcom SPI nodesMichael Walle
Add all the SPI nodes for the flexcom IP block. Keep them disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-6-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add all flexcom usart nodesMichael Walle
Add all the remaining usart nodes for the flexcom block. Although the DMA channels are specified, DMA is not enabled by default because break detection doesn't work with DMA. Keep the nodes disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-5-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add missing uart DMA channelMichael Walle
The usart node of the flexcom3 block is missing the DMA channels. Add it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-4-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: add sgpio nodeMichael Walle
Add the device tree node for the SGPIO IP block reused from the SparX-5. Keep the node disabled by default. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-3-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: swap dma channels for crypto nodeMichael Walle
The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order of the channels. Swap them to pass devicetree validation. Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220502224127.2604333-2-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: lan966x: rename pinctrl nodesMichael Walle
The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220420194230.3415663-1-michael@walle.cc Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: at91: sama7g5: remove interrupt-parent from gic nodeEugen Hristev
interrupt-parent is not to be used as a boolean property. It is already present in the DT in the proper way it's supposed to be used: interrupt-parent = <&gic>; This is also reported by dtbs_check: arch/arm/boot/dts/at91-sama7g5ek.dtb: interrupt-controller@e8c11000: interrupt-parent: True is not of type 'array' From schema: /.local/lib/python3.8/site-packages/dtschema/schemas/interrupts.yaml Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220503133127.64320-1-eugen.hristev@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: at91: use generic node name for dataflashKrzysztof Kozlowski
The node names should be generic, so use "flash" for dataflash nodes and for cfi-flash. Suggested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220412105013.249793-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-13ARM: dts: turris-omnia: Add atsha204a nodePali Rohár
Crypto module atsha204a is available at i2c address 0x64. Module is used for symmetric cryptography and provides also hardware random number generator and OTP storage for device serial number and MAC addresses. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2022-05-13Merge tag 'at91-soc-5.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 & POLARFIRE SoC #1 for 5.19: - Power Management: add possibility to implement specific pm quirks for some SoCs - Kconfig update for AT91 PIT64 and LAN966 low-level debugging - sama5d2: add secure calls to OP-TEE and secure suspend * tag 'at91-soc-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: debug: add lan966 support ARM: at91: pm: add support for sama5d2 secure suspend ARM: at91: add code to handle secure calls ARM: at91: Kconfig: implement PIT64B selection ARM: at91: pm: add quirks for pm ARM: at91: pm: use kernel documentation style ARM: at91: pm: introduce macros for pm mode replacement ARM: at91: pm: keep documentation inline with structure members Link: https://lore.kernel.org/r/20220513121701.77683-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13ARM: configs: Enable ASoC AC'97 glueMark Brown
AC'97 was quite commonly used on at least i.MX designs so enable the glue code that allows use of AC'97 with ASoC based designs to improve testing coverage. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220513120632.168148-1-broonie@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'v5.18-next-defconfig' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/defconfig - Enable essential PMIC and regulatro drivers for MT8195. - Enable Arm arch timer for MT7629. * tag 'v5.18-next-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm: mediatek: select arch timer for mt7629 arm64: defconfig: enable some mt6360 PMIC drivers arm64: defconfig: enable MT6359 regulator driver Link: https://lore.kernel.org/r/3a6e5606-7b89-2ad8-7b45-21d3a4e9e706@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13ARM: at91: debug: add lan966 supportKavyasree Kotagiri
Add support for low-level debugging on FLEXCOM USART of LAN966 SoC. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220513092530.19213-1-kavyasree.kotagiri@microchip.com
2022-05-13Merge tag 'v5.19-rockchip-soc32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/soc Comment typo fix. * tag 'v5.19-rockchip-soc32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: fix typos in comments Link: https://lore.kernel.org/r/4421093.ElGaqSPkdT@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Merge tag 'v5.19-rockchip-dts32-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Naming and flag corrections. * tag 'v5.19-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: rename pcfg_pull_default node name on rk3036 ARM: dts: rockchip: use generic node name for dma rk3036/rk322x ARM: dts: rockchip: correct interrupt flags on rk3188 boards Link: https://lore.kernel.org/r/6919636.31r3eYUQgx@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13Revert "ARM: dts: BCM5301X: Fix DTC warning for NAND node"Arnd Bergmann
This reverts commit 90103611d573, which caused a new DTC warning arch/arm/boot/dts/bcm953012hr.dts:57.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:62.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@200000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:66.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@600000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dts:70.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@1000000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' arch/arm/boot/dts/bcm953012hr.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-12ARM: dts: socfpga: align SPI NOR node name with dtschemaKrzysztof Kozlowski
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-05-12ARM: at91: pm: add support for sama5d2 secure suspendClément Léger
When running with OP-TEE, the suspend control is handled securely. Suspend can be entered using PSCI support. Since the sama5d2 supports multiple suspend modes, add a new CONFIG_ATMEL_SECURE_PM which will send a SMC call to select the suspend mode at init time. "atmel.pm_modes" boot argument is still supported for compatibility purposes but the standby value is actually ignored since PSCI suspend is used and it only support one mode (suspend). Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: add code to handle secure callsClément Léger
Since OP-TEE now has a more complete support for sama5d2, add necessary code to perform SMC calls. The detection of OP-TEE is based on a specific device-tree node path (/firmware/optee) such has done by some other SoC. A check is added to avoid doing SMC calls without having OP-TEE. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: Kconfig: implement PIT64B selectionClaudiu Beznea
Implement PIT64B selection thus it will be available for the necessary targets (at the moment SAM9X60 and SAMA7G5) w/o the necessity to specify it via defconfig. With this the current CONFIG_TIMER_OF dependency of PIT64B driver could be removed. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: add quirks for pmClaudiu Beznea
SoCs supporting ULP0 or ULP1 modes and variants of Cadence Ethernet IP (controlled by macb driver) may behave buggy when Wake-on-Lan (WoL) is configured and WoL packet is received while in ULP0/ULP1. On some SoCs Ethernet interface is not working after resume. On other SoCs the CPU goes to abort on resume path when switching execution from internal SRAM to DRAM. For ULP1 + WoL the issue is related a particular restart sequence of the internal clocks when resuming. These clocks are automatically managed by PMC and may happen that GMAC peripheral clock is restarted few clock cycles before internal clocks causing blocking of Ethernet's DMA. As a consequence Ethernet TX transactions are stopped and RX transactions are partially stopped (packets are received by MAC, RX counters incremented but the data is not transferred to DRAM). The workaround for this is to disable Ethernet's peripheral clock when going to ULP1. Same behavior has been reproduced on ULP0 for some platforms (SAMA5D2, SAMA5D3) and the same workaround solves the issue. The problem has been solved on pm.c as quirk to avoid polluting the MACB driver with AT91 specific issues as this driver is generic to multiple vendors. At probe pointers to struct device_node are retrieved and on the at91_pm_enter() the quirk specifics are applied: for all Ethernet interfaces that were parsed the peripheral clocks are disabled. A special handling is done for modes in dns_modes mask as these are considered modes that blocks the system if WoL packet are received but for which applying quirk will lead to not waking up on WoL packets: in situation where Ethernet interface(s) has suspend mode in dns_modes mask and Ethernet interface(s) is the only available wakeup source the suspend is canceled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: use kernel documentation styleClaudiu Beznea
Use kernel documentation style. Along with it fix the naming of struct at91_pm_sfrbu_regs in documentation. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: introduce macros for pm mode replacementClaudiu Beznea
Introduce macros to replace standby/suspend mode if they depends on controllers that failed to map (or other errors). Macros keep track of the complementary mode to avoid having set the same AT91 PM mode for both suspend and standby. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-12ARM: at91: pm: keep documentation inline with structure membersClaudiu Beznea
Move documentation of bu to keep the same order as in the structure itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2022-05-11swiotlb-xen: fix DMA_ATTR_NO_KERNEL_MAPPING on armChristoph Hellwig
swiotlb-xen uses very different ways to allocate coherent memory on x86 vs arm. On the former it allocates memory from the page allocator, while on the later it reuses the dma-direct allocator the handles the complexities of non-coherent DMA on arm platforms. Unfortunately the complexities of trying to deal with the two cases in the swiotlb-xen.c code lead to a bug in the handling of DMA_ATTR_NO_KERNEL_MAPPING on arm. With the DMA_ATTR_NO_KERNEL_MAPPING flag the coherent memory allocator does not actually allocate coherent memory, but just a DMA handle for some memory that is DMA addressable by the device, but which does not have to have a kernel mapping. Thus dereferencing the return value will lead to kernel crashed and memory corruption. Fix this by using the dma-direct allocator directly for arm, which works perfectly fine because on arm swiotlb-xen is only used when the domain is 1:1 mapped, and then simplifying the remaining code to only cater for the x86 case with DMA coherent device. Reported-by: Rahul Singh <Rahul.Singh@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Rahul Singh <rahul.singh@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Tested-by: Rahul Singh <rahul.singh@arm.com>
2022-05-11Merge branch 'v5.18-rc5'Peter Zijlstra
Obtain the new INTEL_FAM6 stuff required. Signed-off-by: Peter Zijlstra <peterz@infradead.org>
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