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2026-01-17ARM: dts: imx: move nand related property under nand@0Frank Li
Add child node nand@0 and move NAND related property under it to align modern nand-controller.yaml. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected) from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Since 2019 year, commit (212e496935929 dt-bindings: mtd: Add YAML schemas for the generic NAND options) NAND related property is preferred located under nand@<n> even though only one NAND chip supported. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17ARM: dts: imx6sx: update gpmi #size-cells to 0Frank Li
Update gpmi #size-cells to 0 to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: nand-controller@1806000 (fsl,imx6sx-gpmi-nand): #size-cells: 0 was expected from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17ARM: dts: imx6qdl: add '#address-cells' and '#size-cells' for gpmi-nandFrank Li
Add '#address-cells' and '#size-cells' for gpmi-nand to below CHECK_DTBS warings: arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dtb: nand-controller@112000 (fsl,imx6q-gpmi-nand): '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17ARM: tegra: Adjust DSI nodes for Tegra20/Tegra30Svyatoslav Ryhel
Add missing nvidia,mipi-calibrate and cells properties to DSI nodes. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-15crypto: arm/ghash - Use new AES library APIEric Biggers
Switch from the old AES library functions (which use struct crypto_aes_ctx) to the new ones (which use struct aes_enckey). This eliminates the unnecessary computation and caching of the decryption round keys. The new AES en/decryption functions are also much faster and use AES instructions when supported by the CPU. Note that in addition to the change in the key preparation function and the key struct type itself, the change in the type of the key struct results in aes_encrypt() (which is temporarily a type-generic macro) calling the new encryption function rather than the old one. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-24-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-15Merge tag 'at91-fixes-6.19' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes Microchip AT91 fixes for v6.19 This update includes: - fix access to the PHYs on the Microchip LAN966X PCB8290 board - fix the ranges DT property for flexcom9 on the Microchip SAMA7D65 SoC - fix the #size-cells DT property for i2c3 on the Microchip SAMA7D65 SoC * tag 'at91-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: microchip: sama7d65: fix size-cells property for i2c3 ARM: dts: microchip: sama7d65: fix the ranges property for flx9 ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-15ARM: dts: r9a06g032: Add support for GPIO interruptsHerve Codina (Schneider Electric)
In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://patch.msgid.link/20260114093938.1089936-9-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-15ARM: dts: r9a06g032: Add GPIO controllersHerve Codina (Schneider Electric)
Add GPIO controllers (Synopsys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC. Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20260114093938.1089936-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-13ARM: VDSO: Provide clock_getres_time64()Thomas Weißschuh
For consistency with __vdso_clock_gettime64() there should also be a 64-bit variant of clock_getres(). This will allow the extension of CONFIG_COMPAT_32BIT_TIME to the vDSO and finally the removal of 32-bit time types from the kernel and UAPI. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20251223-vdso-compat-time32-v1-7-97ea7a06a543@linutronix.de
2026-01-13ARM: VDSO: Patch out __vdso_clock_getres() if unavailableThomas Weißschuh
The vDSO code hides symbols which are non-functional. __vdso_clock_getres() was not added to this list when it got introduced. Fixes: 052e76a31b4a ("ARM: 8931/1: Add clock_getres entry point") Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20251223-vdso-compat-time32-v1-6-97ea7a06a543@linutronix.de
2026-01-12lib/crypto: arm/aes: Migrate optimized code into libraryEric Biggers
Move the ARM optimized single-block AES en/decryption code into lib/crypto/, wire it up to the AES library API, and remove the superseded "aes-arm" crypto_cipher algorithm. The result is that both the AES library and crypto_cipher APIs are now optimized for ARM, whereas previously only crypto_cipher was (and the optimizations weren't enabled by default, which this fixes as well). Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-11-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-12crypto: aes - Replace aes-generic with wrapper around libEric Biggers
Now that the AES library's performance has been improved, replace aes_generic.c with a new file aes.c which wraps the AES library. In preparation for making the AES library actually utilize the kernel's existing architecture-optimized AES code including AES instructions, set the driver name to "aes-lib" instead of "aes-generic". This mirrors what's been done for the hash algorithms. Update testmgr.c accordingly. Since this removes the crypto_aes_set_key() helper function, add temporary replacements for it to arch/arm/crypto/aes-cipher-glue.c and arch/arm64/crypto/aes-cipher-glue.c. This is temporary, as that code will be migrated into lib/crypto/ in later commits. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-10-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-12crypto: arm/aes - Switch to aes_enc_tab[] and aes_dec_tab[]Eric Biggers
Instead of crypto_ft_tab and crypto_it_tab from aes_generic.c, use aes_enc_tab and aes_dec_tab from lib/crypto/aes.c. These contain the same data in the first 1024 bytes (which is the part that this code uses), so the result is the same. This will allow aes_generic.c to eventually be removed. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-5-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-12crypto: arm/aes-neonbs - Use AES library for single blocksEric Biggers
aes-neonbs-glue.c calls __aes_arm_encrypt() and __aes_arm_decrypt() to en/decrypt single blocks for CBC encryption, XTS tweak encryption, and XTS ciphertext stealing. In preparation for making the AES library use this same ARM-optimized single-block AES en/decryption code and making it an internal implementation detail of the AES library, replace the calls to these functions with calls to the AES library. Note that this reduces the size of the aesbs_cbc_ctx and aesbs_xts_ctx structs, since unnecessary decryption round keys are no longer included. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260112192035.10427-4-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-12lib/crypto: arm/nh: Migrate optimized code into libraryEric Biggers
Migrate the arm32 NEON implementation of NH into lib/crypto/. This makes the nh() function be optimized on arm32 kernels. Note: this temporarily makes the adiantum template not utilize the arm32 optimized NH code. This is resolved in a later commit that converts the adiantum template to use nh() instead of "nhpoly1305". Link: https://lore.kernel.org/r/20251211011846.8179-4-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
2026-01-12arm/paravirt: Use common code for paravirt_steal_clock()Juergen Gross
Remove the arch-specific variant of paravirt_steal_clock() and use the common one instead. This allows to remove paravirt.c and paravirt.h from arch/arm. Until all archs supporting Xen have been switched to the common code of paravirt_steal_clock(), drivers/xen/time.c needs to include asm/paravirt.h for those archs, while this is not necessary for arm any longer. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260105110520.21356-8-jgross@suse.com
2026-01-12sched: Move clock related paravirt code to kernel/schedJuergen Gross
Paravirt clock related functions are available in multiple archs. In order to share the common parts, move the common static keys to kernel/sched/ and remove them from the arch specific files. Make a common paravirt_steal_clock() implementation available in kernel/sched/cputime.c, guarding it with a new config option CONFIG_HAVE_PV_STEAL_CLOCK_GEN, which can be selected by an arch in case it wants to use that common variant. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260105110520.21356-7-jgross@suse.com
2026-01-12paravirt: Remove asm/paravirt_api_clock.hJuergen Gross
All architectures supporting CONFIG_PARAVIRT share the same contents of asm/paravirt_api_clock.h: #include <asm/paravirt.h> So remove all incarnations of asm/paravirt_api_clock.h and remove the only place where it is included, as there asm/paravirt.h is included anyway. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> # powerpc, scheduler bits Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260105110520.21356-6-jgross@suse.com
2026-01-12arm/arm64: dts: renesas: Drop unused .dtsiRob Herring (Arm)
These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251212203226.458694-1-robh@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-10ARM: at91: remove unnecessary of_platform_default_populate callsRob Herring (Arm)
The DT core will call of_platform_default_populate, so it is not necessary for machine specific code to call it unless there are custom match entries, auxdata or parent device. Neither of those apply here, so remove the call. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260105-at91-probe-v3-3-594013ff2965@kernel.org Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-10ARM: at91: Move PM init functions to .init_late hookRob Herring (Arm)
Move the AT91 PM init functions to .init_late hook to ensure driver dependencies have probed. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260105-at91-probe-v3-2-594013ff2965@kernel.org Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-10arm: dts: lpc32xx: add interrupts property to Motor Control PWMVladimir Zapolskiy
Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-10arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree nodeVladimir Zapolskiy
Motor Control PWM depends on its own supply clock, the clock gate control is present in TIMCLK_CTRL1 register. Fixes: b7d41c937ed7 ("ARM: LPC32xx: Add the motor PWM to base dts file") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Add missing properties to I2S device tree nodesPiotr Wojtaszczyk
Add NXP LPC32xx I2S controller device tree properties in accordance to nxp,lpc3220-i2s.yaml. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-7-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> [vzapolskiy: changes to the commit message] Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controllerVladimir Zapolskiy
Add 'lli-bus-interface-ahb2' and 'mem-bus-interface-ahb2' properties to the PL080 DMA controller device tree node, tested with dmatest utility. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Add missing DMA propertiesPiotr Wojtaszczyk
Add properties declared in the new DT binding nxp,lpc3220-dmamux.yaml and corresponding phandles. [vzapolskiy]: 1. rebased the change, 2. dmamux unit address shall be 0x78 instead of 0x7c, 3. removed unsupported 'dmas' properties from sd, ssp0, ssp1 and HS UARTs, 4. more non-functional updates by reordering properies, 5. minor updates to the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-6-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Use syscon for system control blockPiotr Wojtaszczyk
The clock controller is a part of NXP LPC32xx system control block (SCB), and SCB provides a number of controllers apart of the clock controller. [vzapolskiy]: 1. kept a simple comment, 2. renamed SoC specific compatible to 'nxp,lpc3220-scb' due to the SoC UM, 3. changed size in 'ranges', since it should cover more SCB functions, 4. updated the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-5-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controllerVladimir Zapolskiy
SLC and MLC NAND flash controllers fire the muxed interrupt FLASH_INT to the SoC, add the interrupt property to the SLC device tree node. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: change NAND controllers node namesVladimir Zapolskiy
The device tree node name of NAND controllers shall be 'nand-controller', while 'flash' name is the name of NAND chip device tree nodes. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Update spi clock propertiesKuldeep Singh
PL022 binding require two clocks to be defined but NXP LPC32xx platform doesn't comply with the bindings and define only one clock i.e apb_pclk. Update SPI clocks and clocks-names property by adding appropriate clock reference to make it compliant with the bindings. Noteworthy, strictly speaking the change tackles DT ABI by changing the order in the list of clock-names property values, however this level of impact is considered as acceptable. Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> [vzapolskiy: rebased and minor update to the commit message] Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: Add support for pcb8385Horatiu Vultur
Add basic support for pcb8385 [1]. It is a modular board which allows to add different daughter cards on which there are different PHYs. This adds support for UART, LEDs and I2C. [1] https://www.microchip.com/en-us/development-tool/ev83e85a Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20251208083545.3642168-3-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08ARM: dts: broadcom: bcm2711: Fix 'simple-bus' node namesRob Herring (Arm)
Fix 'simple-bus' node names to follow the defined pattern. Nodes with 'reg' or 'ranges' addresses should also have a unit-address. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-1-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2026-01-08ARM: dts: stm32: reorder nodes for stm32429i-evalPatrice Chotard
Reorder nodes by alphabetical order. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-1-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2026-01-08ARM: dts: aspeed: ibm: Use non-deprecated AT25 propertiesRob Herring (Arm)
The at25,* properties have been deprecated since 2012. These platforms weren't upstream until 2020 and 2023, so it should be safe to switch over to the "new" properties and just drop the deprecated ones. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08ARM: dts: microchip: sama7d65: add missing flexcom nodesNicolas Ferre
Add nodes for usart, spi and i2c when missing to the flexcom nodes. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20260102170135.70717-6-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08ARM: dts: microchip: sama7d65: add fifo-size to usartNicolas Ferre
When missing, add the atmel,fifo-size = <32> property for usart nodes in flexcom. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20260102170135.70717-5-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08ARM: dts: microchip: sama7d65: add dma properties to usart6Nicolas Ferre
Add the dma property and associated dma activation for usart6 as part of flx6 node. Is useful for usual default console on this product. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20260102170135.70717-4-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08ARM: dts: microchip: sama7d65: fix size-cells property for i2c3Nicolas Ferre
Fix the #size-cells property for i2c3 node and remove the dtbs_check error telling that "#size-cells: 0 was expected" from schema atmel,at91sam-i2c.yaml and i2c-controller.yaml. Fixes: b51e4aea3ecf ("ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoC") Cc: stable@vger.kernel.org # 6.16+ Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20260102170135.70717-3-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08ARM: dts: microchip: sama7d65: fix the ranges property for flx9Hari Prasath Gujulan Elango
Update the ranges property for the flexcom9 as per the datasheet and align with the reg property. Fixes: b51e4aea3ecf ("ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d65 SoC") Cc: stable@vger.kernel.org # 6.16+ Signed-off-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20260102170135.70717-2-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-08arm: npcm: drop unused Kconfig ERRATA symbolRandy Dunlap
The code for this errata was not merged. See https://lore.kernel.org/linux-arm-kernel/CAL_JsqK--G_7nO_UQ6jyomA1Sq6GUKtXVZpBF0dXjYA2iE047w@mail.gmail.com/ Fixes: 7bffa14c9aed ("arm: npcm: add basic support for Nuvoton BMCs") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMCRebecca Cran
The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Tested-by: Tan Siewert <tan.siewert@hetzner.com> Reviewed-by: Tan Siewert <tan.siewert@hetzner.com> Link: https://patch.msgid.link/20251218161816.38155-3-rebecca@bsdio.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08ARM: dts: aspeed: bletchley: Remove try-power-role from connectorsCosmo Chou
Remove the "try-power-role = sink" property from all USB-C connectors. The try mechanism is unnecessary and wastes time during connection. Since power-role = "dual" is already configured, standard USB PD negotiation is sufficient and more efficient. Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08ARM: dts: aspeed: Add Facebook Anacapa platformPeter Shen
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray. This platform is a key component of the AMD Helios AI rack reference design system, designed for next-generation AI workloads. The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom OCP NIC) and host CPUs. Its primary role is to provide essential system control, power sequencing, and telemetry reporting for the compute complex via the OpenBMC software stack. For more detail on the AMD Helios reference design: https://www.amd.com/en/blogs/2025/amd-helios-ai-rack-built-on-metas-2025-ocp-design.html Signed-off-by: Peter Shen <sjg168@gmail.com> Link: https://patch.msgid.link/20251219091632.1598603-3-sjg168@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-07Merge tag 'renesas-dts-for-v6.20-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.20 - Add USB3.2 host and more RSCI serial support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board, - Add display and USB3.0 host support for the RZ/V2H and RZ/V2N SoCs and their EVK boards, - Add SPI NOR Flash support for the Yuridenki-Shokai Kakip board, - Add PCIe support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board, - Add SPI, interrupt controller, and DMAC support for the RZ/T2H, RZ/N2H, and RZ/V2N SoCs, - Add NMI wakeup button support for the RZ/V2N EVK board, - Add thermal support for the RZ/V2N SoC, - Add system watchdog timer support for R-Car V3H, which is reserved for secure firmware, - Add window watchdog timer support for R-Car V3M, V3H, and Gen4 SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (41 commits) arm64: dts: renesas: r8a779h0: Add WWDT nodes arm64: dts: renesas: r8a779g0: Add WWDT nodes arm64: dts: renesas: r8a779f0: Add WWDT nodes arm64: dts: renesas: r8a779a0: Add WWDT nodes arm64: dts: renesas: r8a77980: Add WWDT nodes arm64: dts: renesas: r8a77970: Add WWDT nodes arm64: dts: renesas: condor/v3hsk: Mark SWDT as reserved arm64: dts: renesas: r8a77980: Add SWDT node arm64: dts: renesas: r9a09g056: Add TSU nodes arm64: dts: renesas: r9a09g087: Add DMAC support arm64: dts: renesas: r9a09g077: Add DMAC support arm64: dts: renesas: r9a09g087: Add ICU support arm64: dts: renesas: r9a09g077: Add ICU support arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodes arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS arm64: dts: renesas: r9a09g047: Add RSCI nodes ARM: dts: renesas: r9a06g032: Add Ethernet switch interrupts arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support arm64: dts: renesas: r9a09g056: Add RSPI nodes arm64: dts: renesas: r9a09g056: Add DMAC nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07Merge tag 'imx-fixes-6.19' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.19: - A mba8mx fix from Alexander Stein to correct Ethernet PHY IRQ trigger type - An i.MX95 fix from Carlos Song to correct I3C2 pclk - A couple of imx8qm-mek changes from Haibo Chen to fix light sensor interrupt type and usdhc2 regulator configuration - An imx6q-ba16 change from Ian Ray to fix RTC interrupt level - An imx8mp-dhcom-som change from Marek Vasut to fix sporadic Ethernet link bouncing caused by interruptions on the PHY reference clock - A couple of imx8mp-tx8p changes from Maud Spierings to fix compatible and eqos nvmem-cells - An ARM i.MX fix from Rob Herring to correct mc13xxx LED node names - An imx8qm-ss-dma change from Sherry Sun to correct DMA channels for LPUART - A couple of imx95-toradex-smarc changes from Vitor Soares to fix ethphy1 interrupt and SMARC_SDIO_WP label position * tag 'imx-fixes-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: mba8mx: Fix Ethernet PHY IRQ support arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells arm64: dts: freescale: moduline-display: fix compatible dt-bindings: arm: fsl: moduline-display: fix compatible ARM: dts: imx6q-ba16: fix RTC interrupt level arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt arm64: dts: add off-on-delay-us for usdhc2 regulator arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level ARM: dts: nxp: imx: Fix mc13xxx LED node names arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-07ARM: dts: meson: drop iio-hwmon in favour of generic-adc-thermalMartin Blumenstingl
Commit 85b21fdec906e ("thermal/drivers/generic-adc: Register thermal zones as hwmon sensors") made "generic-adc-thermal" also register hwmon attributes. That means we now have the temperature sensor shown twice: - once from iio-hwmon - and another time from generic-adc-thermal We need the latter for SoC temperature control, so simply drop the former so userspace doesn't see duplicate sensors. Also generic-adc-thermal provides a better name to userspace ("soc_thermal-virtual-0") than iio_hwmon. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://patch.msgid.link/20251108211503.1578711-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-01-07ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" propertyChen-Yu Tsai
The P66's device tree includes the reference design dtsi files, which defines a node and properties for the touchpanel in the common design. The P66 dts file then overrides all the properties to match its own design, but as the touchpanel model is different, a different schema is matched. This other schema uses a different name for the GPIO. The original submission added the correct GPIO property, but did not delete the one inherited from the reference design, causing validation errors. Explicitly delete the incorrect GPIO property. Fixes: 2a53aff27236 ("ARM: dts: sun5i: Enable touchscreen on Utoo P66") Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251225103616.3203473-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-01-06arm/uprobes: use kmap_local_page() in arch_uprobe_copy_ixol()Keke Ming
Replace deprecated kmap_atomic() with kmap_local_page(). Signed-off-by: Keke Ming <ming.jvle@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Oleg Nesterov <oleg@redhat.com> Link: https://patch.msgid.link/20260103084243.195125-5-ming.jvle@gmail.com
2026-01-05ARM: dts: omap: dra7: Remove bogus #syscon-cells propertyVladimir Zapolskiy
There is no such dt binding property as '#syscon-cells', remove it. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Link: https://patch.msgid.link/20251230234040.2083889-1-vz@mleia.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2026-01-05ARM: omap1: drop unused Kconfig symbolRandy Dunlap
"select ARCH_HAS_HOLES_MEMORYMODEL" was mistakenly merged here due to a botched rebase (says Arnd [1]). Drop that line since that symbol is not used anywhere else in the kernel source tree. [1] https://lore.kernel.org/all/5e335232-89b4-4c35-93bd-efad7e4d8995@app.fastmail.com/ Fixes: 7036440eab3e ("ARM: omap1: enable multiplatform") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Aaro Koskinen <aaro.koskinen@iki.fi> Link: https://patch.msgid.link/20251230055230.3212260-1-rdunlap@infradead.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-16 13:48:14 +0000