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2025-01-02KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bitsMarc Zyngier
Allow a guest hypervisor to trap accesses to CNT{P,V}CT_EL02 by propagating these trap bits to the host trap configuration. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-10-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT}Marc Zyngier
For completeness, fun, and cerebral meltdown, add the virtualisation related traps to the counter and timers. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-9-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: Handle counter access early in non-HYP contextMarc Zyngier
We already deal with CNTPCT_EL0 accesses in non-HYP context. Let's add CNTVCT_EL0 as a good measure. This is also an opportunity to simplify things and make it plain that this code is only for non-HYP context handling. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-8-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor contextMarc Zyngier
Similarly to handling the physical timer accesses early when FEAT_ECV causes a trap, we try to handle the physical counter without returning to the general sysreg handling. More surprisingly, we introduce something similar for the virtual counter. Although this isn't necessary yet, it will prove useful on systems that have a broken CNTVOFF_EL2 implementation. Yes, they exist. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-7-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in useMarc Zyngier
Although FEAT_ECV allows us to correctly emulate the timers, it also reduces performances pretty badly. Mitigate this by emulating the CTL/CVAL register reads in the inner run loop, without returning to the general kernel. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-6-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timersMarc Zyngier
Although FEAT_NV2 makes most things fast, it also makes it impossible to correctly emulate the timers, as the sysreg accesses are redirected to memory. FEAT_ECV addresses this by giving a hypervisor the ability to trap the EL02 sysregs as well as the virtual timer. Add the required trap setting to make use of the feature, allowing us to elide the ugly resync in the middle of the run loop. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-5-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory stateMarc Zyngier
With FEAT_NV2, the EL0 timer state is entirely stored in memory, meaning that the hypervisor can only provide a very poor emulation. The only thing we can really do is to publish the interrupt state in the guest view of CNT{P,V}_CTL_EL0, and defer everything else to the next exit. Only FEAT_ECV will allow us to fix it, at the cost of extra trapping. Suggested-by: Chase Conklin <chase.conklin@arm.com> Suggested-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com> Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Sync nested timer state with FEAT_NV2Marc Zyngier
Emulating the timers with FEAT_NV2 is a bit odd, as the timers can be reconfigured behind our back without the hypervisor even noticing. In the VHE case, that's an actual regression in the architecture... Co-developed-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-3-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02KVM: arm64: nv: Add handling of EL2-specific timer registersMarc Zyngier
Add the required handling for EL2 and EL02 registers, as well as EL1 registers used in the E2H context. This includes handling the virtual timer accesses when CNTHCTL_EL2.EL1TVT or CNTHCTL_EL2.EL1TVCT are set. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-2-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-01-02arm64: dts: ti: k3-j7200: Add node to disable loopback connectionAnurag Dutta
CTRLMMR_MCU_SPI1_CTRL register controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out. By default, the field SPI1_LINKDIS (Bit 0) is set to 0h. In order to disable the direct connection, the SPI1_LINKDIS (Bit 0) needs to be set to 1h. Model this functionality as a "reg-mux" device and based on the idle-state property, enable/disable the connection bewtween MCU_SPI1 and MAIN_SPI3. The register field description has been referred from J7200 TRM [1] (Table 5-517. CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions). [1] https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Anurag Dutta <a-dutta@ti.com> Link: https://lore.kernel.org/r/20241127075644.210759-1-a-dutta@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-j784s4: Use ti,j7200-padconf compatibleThomas Richard
Like on j7200, pinctrl contexts shall be saved and restored during suspend-to-ram. So use ti,j7200-padconf compatible. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20241230-j784s4-s2r-pinctrl-v2-1-35039fafe2ca@bootlin.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62p-j722s-common-main: Enable USB0 for DFU bootSiddharth Vadapalli
Add the "bootph-all" property to the "usb0" device-tree node. This is required for the USB0 instance of USB to be functional at all stages of USB DFU boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241220054550.153360-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62a: Remove duplicate GICR regBryan Brattlof
The GIC Redistributor control range is mapped twice. Remove the extra entry from the reg range. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-2-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62: Remove duplicate GICR regBryan Brattlof
The GIC Redistributor control register range is mapped twice. Remove the extra entry from the reg range. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20241210-am62-gic-fixup-v1-1-758b4d5b4a0a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am67a-beagley-ai: Add remote processor nodesAndrew Davis
Add nodes for the R5F and C7x cores on the SoC. This includes the mailbox and memory carveouts used by these remote cores. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203174114.94751-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62p: Enable Mailbox nodes at the board levelAndrew Davis
Mailbox nodes defined in the top-level J722s/AM62p SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203174114.94751-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am625-sk: Remove M4 mailbox node redefinitionAndrew Davis
This node is already defined in the included k3-am62x-sk-common.dtsi. Remove this redefinition. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20241203164031.20211-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-j722s-evm: Enable support for mcu_i2c0Bhavya Kapoor
Enable support for mcu_i2c0 and add pinmux required to bring out the mcu_i2c0 signals on 40-pin RPi expansion header on the J722S EVM. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Signed-off-by: Shreyash Sinha <s-sinha@ti.com> Reviewed-by: Prasanth Babu Mantena <p-mantena@ti.com> Link: https://lore.kernel.org/r/20241105091224.23453-1-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-01-02arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in ↵Chintan Vankar
cpsw_mac_syscon node Ethernet boot requires CPSW node to be present starting from R5 SPL stage. Add bootph-all property in CPSW MAC's eFuse node cpsw_mac_syscon to enable this node during SPL stage along with later boot stages so that CPSW port will get static MAC address. Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com> Link: https://lore.kernel.org/r/20241114165331.1279065-1-c-vankar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-12-30arm64: dts: freescale: imx93-9x9-qsb: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-14x14-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-11x11-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95-19x19-evk: add ENETC 0 supportWei Fang
Add ENETC 0 (1G ethernet port) support for i.MX95-19x19-EVK board. In addition, because all ENETC instances share MDIO bus, so enable EMDIO at the same time. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95: add NETC related nodesWei Fang
Add NETC related nodes for i.MX95. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mm-phg: Add LVDS compatible stringFabio Estevam
The imx8mm-phg board has an AUO G084SN05 V9 8.4" 800x600 LVDS panel. Improve the devicetree description by passing the LVDS compatible string to fix the following dt-schema warning: imx8mm-phg.dtb: panel: compatible:0: 'panel-lvds' is not one of ['admatec,9904379', 'auo,b101ew05', 'auo,g084sn05', 'chunghwa,claa070wp03xg','edt,etml0700z9ndha', 'hannstar,hsd101pww2', 'hydis,hv070wx2-1e0', 'jenson,bl-jt60050-01a', 'tbs,a711-panel'] ... Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: exynos8895: Add camera hsi2c nodesIvaylo Ivanov
Add nodes for hsi2c1-4 (CAM0-3), which allows using them. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241221152803.1663820-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30arm64: dts: exynos990: Add clock management unit nodesIgor Belwon
Add CMU nodes for: - cmu_top: provides clocks for other blocks - cmu_hsi0: provides clocks for usb31 Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241224-cmu-v3-1-33ca24b2413c@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30arm64: dts: imx93: add pca9452 supportJoy Zou
Support pca9452 on imx93-14x14-evk. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mn-bsh-smm-s2/pro: add simple-framebufferDario Binacchi
Add a simple-framebuffer node for U-Boot to further fill and activate. Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-29arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmodeAndré Draszik
When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCiAndré Draszik
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-27arm64: dts: qcom: x1e80100: Fix interconnect tags for SDHC nodesAbel Vesa
The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the active-only tags. The tags are missing entirely on for the SDHC_4 controller interconnect paths. Fix all tags for both controllers. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241227-b4-x1e80100-qcp-sdhc-fixes-v1-1-cd971f7f0955@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qrb4210-rb2: add HDMI audio playback supportAlexey Klimov
Add sound node and dsp-related piece to enable HDMI audio playback support on Qualcomm QRB4210 RB2 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-5-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm4250: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-4-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112025306.712122-3-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add apr and its servicesAlexey Klimov
Add apr (asynchronous packet router) node and its associated services required to enable audio on QRB4210 RB2 platform. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-2-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: Fix CDSP context banks unit addressesKrzysztof Kozlowski
There is a mismatch between 'reg' property and unit address for last there CDSP compute context banks. Current values were taken as-is from downstream source. Considering that 'reg' is used by Linux driver as SID of context bank and that least significant bytes of IOMMU value match the 'reg', assume the unit-address is wrong and needs fixing. This also won't have any practical impact, except adhering to Devicetree spec. Fixes: dae8cdb0a9e1 ("arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241104144204.114279-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi fileDmitry Baryshkov
The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-21-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi fileDmitry Baryshkov
The SDM670 devices define XO and clocks completely in the board files, despite sdm670.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-20-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sc8180x: drop extra XO clock frequenciesDmitry Baryshkov
sc8180x.dtsi already defines 38.4 MHz clock frequency for the XO clock. Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: x1e80100: correct sleep clock frequencyDmitry Baryshkov
The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: correct sleep clock frequencyDmitry Baryshkov
The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8550: correct sleep clock frequencyDmitry Baryshkov
The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8450: correct sleep clock frequencyDmitry Baryshkov
The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8350: correct sleep clock frequencyDmitry Baryshkov
The SM8350 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8250: correct sleep clock frequencyDmitry Baryshkov
The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6375: correct sleep clock frequencyDmitry Baryshkov
The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6125: correct sleep clock frequencyDmitry Baryshkov
The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-08 04:08:34 +0000