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2021-12-09ARM: dts: am437x-gp-evm: enable ADC1Miquel Raynal
ADC0 and ADC1 pins are available on external connector J22. Enable ADC1 which was missing. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware moduleMiquel Raynal
This hardware module is close to the am33xx ADC module but instead of featuring a touchscreen it has a magnetic reader capability. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09ARM: dts: am437x-cm-t43: Use a correctly spelled DT propertyMiquel Raynal
Back in 2014 a property got misspelled "ti,coordiante-readouts" instead of "ti,coordinate-readouts". The year after it got fixed but both are still supported, although this is not a reason to continue using this old deprecated property. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09ARM: dts: am335x-icev2: Add system-power-controller to RTC nodeDrew Fustini
On the am335x-icev2 board [1], AM3359 PMIC_PWR_EN (ZCZ ball C6) is connected to PWRHOLD (pin 1) on the TPS65910A3 PMIC. The addition of system-power-controller to the rtc node will enable the capability of the RTC driver to poweroff the board. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [2]. [1] https://www.ti.com/tool/TMDSICE3359 [2] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Dave Gerlach <d-gerlach@ti.com> Cc: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold <johan@kernel.org> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09ARM: dts: am335x-boneblack-common: move system-power-controllerDrew Fustini
Move the rtc node system-power-controller property from am335x-boneblack-common.dtsi to am335x-bone-common.dtsi. am335x-boneblack-common.dtsi is included by am335x-boneblack.dts, am335x-boneblack-wireless.dts, am335x-sancloud-bbe.dts and am335x-sancloud-bbe-lite.dts. All of these dts files also include am335x-bone-common.dtsi and thus will retain the rtc node system-power-controller property. am335x-bone-common.dtsi is also included by am335x-bone.dts [1], am335x-bonegreen.dts [2] and am335x-bonegreen-wireless.dts [3]. These boards will now have the rtc node system-power-controller property too. This is valid as they also have PMIC_POWR_EN (ZCZ C6) connected to PWR_EN on the TPS65217B PMIC. Based on commit 15c7be47fb7c ("ARM: dts: am335x: Add rtc node as system-power-controller") by Keerthy in ti-linux-5.4.y branch [4]. [1] https://beagleboard.org/static/beaglebone/BEAGLEBONE_SCHEM_A3.pdf [2] https://github.com/SeeedDocument/BeagleBone_Green/blob/master/resources/BEAGLEBONE_GREEN_V1.pdf [3] https://github.com/SeeedDocument/BeagleBone_Green_Wireless/blob/master/resources/BeagleBone_Green%20Wireless_V1.0_SCH_20160314.pdf [4] git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Dave Gerlach <d-gerlach@ti.com> Cc: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/linux-omap/20211012191311.879838-1-dfustini@baylibre.com/ Suggested-by: Johan Hovold <johan@kernel.org> Reviewed-by: Johan Hovold <johan@kernel.org> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-09ARM: dts: elpida_ecb240abacn: Change Elpida compatibleDmitry Osipenko
Vendor prefix shouldn't start with capital letter. The Elpida Memory compatible was never used in practice, hence just correct the compatible. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-08ARM: dts: at91: add Microchip EVB-KSZ9477 boardOleksij Rempel
Add KSZ9477 managed switch evaluation kit with SAMA5D36 MPU: https://www.microchip.com/en-us/development-tool/evb-ksz9477 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211111081045.711323-1-o.rempel@pengutronix.de
2021-12-08ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrlMihai Sain
I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is tied with 10K resistor to GND. U13 switch S1 is always selected as voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash. Removing PA11 from pinctrl because it remains unused. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com
2021-12-08ARM: dts: imx6dl-yapp4: Add Y Soft IOTA Crux/Crux+ boardMichal Vokáč
Add devicetrees for the new boards in the Y Soft IOTA family. These boards are based on Orion but use Quad/QuadPlus SoC instead of DualLite. Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08ARM: dts: at91: update alternate function of signal PD20Hari Prasath
The alternate function of PD20 is 4 as per the datasheet of sama7g5 and not 5 as defined earlier. Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com> Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Cc: <stable@vger.kernel.org> # v5.15+ Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com
2021-12-08ARM: dts: sun8i: r40: add node for CAN controllerEvgeny Boger
Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The controller is the same as in earlier A10 and A20 SoCs, but needs reset line to be deasserted before use. This patch adds a CAN node and the corresponding pinctrl descriptions. Link: https://lore.kernel.org/all/20211122104616.537156-4-boger@wirenboard.com Signed-off-by: Evgeny Boger <boger@wirenboard.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2021-12-07ARM: dts: aspeed: add device tree for YADRO VEGMAN BMCAndrei Kartashev
YADRO VEGMAN is x86 based servers family with ASPEED AST2500-based BMC. Currently there are three models: * VEGMAN N110 * VEGMAN S220/320 * VEGMAN R120/220 The dts files provides configuration for BMC system. Signed-off-by: Andrei Kartashev <a.kartashev@yadro.com> Link: https://lore.kernel.org/r/20211119120057.12118-3-a.kartashev@yadro.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-06ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OFJagan Teki
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM) i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2Jagan Teki
Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with 7" LVDS panel. Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. This patch adds a display pipeline to connect DSI to SN65DSI84 to 7" LVDS panel. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-12-06ARM: dts: exynos: Rename hsi2c nodes to i2c for Exynos5260Sam Protsenko
In Device Tree specification it's recommended to use "i2c" name for I2C nodes. Now that i2c-exynos5 dt-schema binding was added, it shows some warnings like this when validating HS-I2C nodes: hsi2c@xxxxxxxxx: $nodename:0: 'hsi2c@xxxxxxxx' does not match '^i2c(@.*)?' From schema: Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Rename hsi2c@* to i2c@* to fix those warnings. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204215820.17378-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-06ARM: dts: imx6ull-pinfunc: Fix CSI_DATA07__ESAI_TX0 pad nameFabio Estevam
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may have the ESAI_TX0 functionality, not ESAI_T0. Also, NXP's i.MX Config Tools 10.0 generates dtsi with the MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly. There are no devicetree users in mainline that use the old name, so just remove the old entry. Fixes: c201369d4aa5 ("ARM: dts: imx6ull: add imx6ull support") Reported-by: George Makarov <georgemakarov1@gmail.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: Add Goramo MultiLink device treeLinus Walleij
This adds a device tree for the Goramo MultiLink IXP425-based WAN router. Cc: Krzysztof Hałasa <khalasa@piap.pl> Cc: openwrt-devel@lists.openwrt.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: Add FSG3 system controller and LEDsLinus Walleij
This adds the system controller on CS2 and the LEDs on it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-06ARM: dts: imx6qdl: add TQ-Systems MBa6x device treesMarkus Niebel
Add device trees for the MBa6x mainboard with TQMa6Q/QP/DL SoMs. As discussed, all new files are added with GPL-2.0-only license, as they are too tightly intertwined with the SoC DTSIs imx6dl.dtsi and imx6q.dtsi, which are GPL-2.0. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: imx6qdl-tqma6: add ERR006687 hardware workaround for "a" variantMatthias Schiffer
The TQMa6x "a" has a workaround for ERR006687 implemented in hardware. Add the required pinmuxing and related setup to make use of this. As board DTS files based on the TQMa6x SoMs will define their own pinmuxing for the FEC ethernet controller as well, we can't apply this pin group unconditionally; instead, it is the responsibility of the board DTs derived from imx6qdl-tqma6a.dtsi to include this group. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06ARM: dts: add JOZ Access PointOleksij Rempel
JOZ Access Point is imx6ull based device designed for agricultural cleaning machines. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-03ARM: socfpga: dts: fix qspi node compatibleDinh Nguyen
The QSPI flash node needs to have the required "jedec,spi-nor" in the compatible string. Fixes: 1df99da8953 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-12-03ARM: decompressor: disable stack protectorArd Biesheuvel
Enabling the stack protector in the decompressor is of dubious value, given that it uses a fixed value for the canary, cannot print any output unless CONFIG_DEBUG_LL is enabled (which relies on board specific build time settings), and is already disabled for a good chunk of the code (libfdt). So let's just disable it in the decompressor. This will make it easier in the future to manage the command line options that would need to be removed again in this context for the TLS register based stack protector. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
2021-12-01ARM: dts: sun8i: Adjust power key nodesJernej Skrabec
Several H3 and one H2+ board have power key nodes, which are slightly off. Some are missing wakeup-source property and some have BTN_0 code assigned instead of KEY_POWER. Adjust them, so they can function as intended by designer. Co-developed-by: Michael Klein <michael@fossekall.de> Signed-off-by: Michael Klein <michael@fossekall.de> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211129165510.370717-1-jernej.skrabec@gmail.com
2021-11-30ARM: dts: qcom: sdx55-t55: Enable IPAManivannan Sadhasivam
Enable IP Accelerator (IPA) on Thundercomm T55 board for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-7-manivannan.sadhasivam@linaro.org
2021-11-30ARM: dts: qcom: sdx55-fn980: Enable IPAManivannan Sadhasivam
Enable IP Accelerator (IPA) on Telit FN980 TLB for getting data connectivity from modem. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-6-manivannan.sadhasivam@linaro.org
2021-11-30ARM: dts: qcom: sdx55-fn980: Enable PCIe EPManivannan Sadhasivam
Enable PCIe Endpoint controller on the Telit FN980 TLB board based on Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org
2021-11-30ARM: dts: qcom: sdx55: Add support for PCIe EPManivannan Sadhasivam
Add support for PCIe Endpoint controller on the Qualcomm SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-4-manivannan.sadhasivam@linaro.org
2021-11-30ARM: dts: qcom: sdx55-fn980: Enable PCIE0 PHYManivannan Sadhasivam
Enable PCIE0 PHY on Telit FN980 TLB for PCIE EP. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-3-manivannan.sadhasivam@linaro.org
2021-11-30ARM: dts: qcom: sdx55: Add support for PCIe PHYManivannan Sadhasivam
Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211126070520.28979-2-manivannan.sadhasivam@linaro.org
2021-11-29ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dkFabrice Gasnier
A pinctrl handle is used to setup a pull-up on the stusb1600 IRQ pin (that is open drain). When in ANALOG state, no pull-up can be applied in the GPIO HW controller, still the setting is done into the register. The pull-up is effective currently, only when the GPIO IRQ is requested. The correct setting is to use directly the GPIO, instead of ANALOG state. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-25ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1Fabrice Gasnier
This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-25ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkxFabrice Gasnier
This patch adds phy tuning parameters for usbphyc port0 (USBH controller) and usbphyc port1 (OTG controller). Phy tuning parameters are used to adjust the phy settings to compensate parasitics, which can be due to USB receptacle, routing, and ESD protection component. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-25ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15Erwan Le Ray
Clean useless spaces in uart4_idle_pins_a node. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-25ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boardsErwan Le Ray
Add pull-up to USART3 and UART7 RX pins to allow loop tests between USART3 and UART7 on stm32mp15 DKx boards. Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-25ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 ↵Dillon Min
disco Since the compatible string defined from ilitek,ili9341.yaml is "st,sf-tc240t-9370-t", "ilitek,ili9341" so, append "ilitek,ili9341" to avoid the below dtbs_check warning. arch/arm/boot/dts/stm32f429-disco.dt.yaml: display@1: compatible: ['st,sf-tc240t-9370-t'] is too short Fixes: a726e2f000ec ("ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board") Signed-off-by: Dillon Min <dillon.minfei@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-11-23ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY bindingRafał Miłecki
The new binding covers a single reg and uses syscon to reference shared register. References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-11-23ARM: dts: ux500: Fixup Gavini magnetometerLinus Walleij
The Gavini device tree had the wrong magnetometer specified, this should be a YAS530. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-11-23ARM: dts: imx: Fix typo in pinfunc commentsJason Wang
Remove the repeated `configurable' in some comments in imx1-pinfunc.h and imx27-pinfunc.h. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23ARM: dts: sunxi: h3/h5: Update MBUS nodeSamuel Holland
In order to support memory dynamic frequency scaling (MDFS), the MBUS binding now requires enumerating more resources. Provide them in the device tree. Since the H3 and H5 have different clock divider limits, they need separate compatibles. Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211118031841.42315-5-samuel@sholland.org
2021-11-23ARM: dts: ux500: Add reset lines to IP blocksLinus Walleij
The new reset controller makes is possible to add reset lines to a host of IP blocks in the DB8500/U8500. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-11-22ARM: dts: milbeaut: set clock phandle to uart nodeSugaya Taichi
Set clock phandle to uart node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Link: https://lore.kernel.org/r/1636968656-14033-4-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-22ARM: dts: milbeaut: set clock phandle to timer nodeSugaya Taichi
Set clock phandle to timer node for Milbeaut M10V support. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Link: https://lore.kernel.org/r/1636968656-14033-3-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-22ARM: dts: milbeaut: add a clock node for M10VSugaya Taichi
Add a clock node for the platform of the Milbeaut M10V. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Link: https://lore.kernel.org/r/1636968656-14033-2-git-send-email-sugaya.taichi@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-22ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC nodeJernej Skrabec
Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has dedicated GPIO pin for that purpose. Add a node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211120102024.439456-1-jernej.skrabec@gmail.com
2021-11-22ARM: dts: sunxi: Add CEC clock to DW-HDMIJernej Skrabec
Experimentation determined that HDMI CEC controller inside DW HDMI block depends on 32k clock from RTC. If this clock is tampered with, HDMI CEC communication starts or stops working, depending on situation. SoC user manual doesn't say anything about CEC, so this was overlooked. Fix this by adding dependency to RTC 32k clock. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211120073448.32480-3-jernej.skrabec@gmail.com
2021-11-22ARM: dts: sun8i: h3: beelink-x2: Sort nodesJernej Skrabec
Nodes are not sorted alphabetically. Do it. There is no functional change. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211121070321.601659-1-jernej.skrabec@gmail.com
2021-11-21ARM: dts: vf610-zii-dev-rev-b: specify phy-mode for external PHYsRussell King (Oracle)
Specify the phy-mode for the external PHYs on the third switch on the ZII development rev B board so phylink and phylib knows what mode these interfaces are configured for. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-21ARM: dts: vf610-zii-dev-rev-b: correct phy-mode for 6185 dsa linkRussell King (Oracle)
DT currently lists the port mode for the 88E6352 switch 1 to 88E6185 switch 2 as "rgmii-id" but referring to the schematics, it is in fact a serdes link. The 88E6352 is configured with P5_MODE=6, S_SEL=1 and S_MODE=1, which means port 5 is configured as 1000BASE-X. This is confirmed by the value in the 88E6352 port 5 status register, 0x4e09, where C_MODE=9 meaning 1000BASE-X. It is also confirmed by the 88E6185 port 9 status register, 0x5e8c, where C_MODE=4 meaning cross-chip SERDES mode is selected. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-21ARM: dts: ls1021a-tsn: update RGMII delays for sja1105 switchVladimir Oltean
In the new behavior, the sja1105 driver expects there to be explicit RGMII delays present on the fixed-link ports, otherwise it will complain that it falls back to legacy behavior, which is to apply RGMII delays incorrectly derived from the phy-mode string. In this case, the legacy behavior of the driver is to not apply delays in any direction (mostly because the SJA1105T can't do that, so this board uses PCB traces). To preserve that but also silence the driver, use explicit delays of 0 ns. The delay information from the phy-mode is ignored by new kernels (it's still RGMII as long as it's "rgmii*" something), and the explicit {rx,tx}-internal-delay-ps properties are ignored by old kernels, so the change works both ways. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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