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2025-07-04ARM: dts: stm32: add stm32mp157f-dk2 board supportAmelie Delaunay
STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same level of feature than a STM32MP157C SOC but A7 clock frequency can reach 800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi. As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE SCMI services for SoC clock and reset controllers resources, and for PMIC, now under OP-TEE control. That's why stm32mp157f-dk2-scmi.dtsi is introduced, to move all clocks, resets and regulators to SCMI-based ones. To "disable" SCMI, just need to comment stm32mp157f-dk2-scmi.dtsi inclusion and to replace &scmi_v3v3 with &v3v3, then to disable arm_wdt and to enable i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for dual role with type-C support if needed. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-7-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: optee async notif interrupt for MP15 scmi variantsEtienne Carriere
Define the interrupt used by OP-TEE async notif on stm32mp15 scmi based platforms. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-5-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use internal regulators bindings for MP15 scmi variantsAmelie Delaunay
Use the SCMI voltage domain bindings for internal regulators on stm32mp15. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-4-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkxAmelie Delaunay
Adopt generic node name 'typec' for stusb1600, which is the USB Type-C controller on stm32mp157x Discovery Kits. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-2-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCsAlexandre Torgue
This commit creates new file to manage security features and supported OPP on STM32MP15xF SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot + A7-CPU@650MHz. -Y = C means cryp IP + optee + secure boot + A7-CPU@650MHz. -Y = D means no cryp IP and no secure boot + A7-CPU@800MHz. -Y = F means cryp IP + optee + secure boot + A7-CPU@800MHz. It fullfills the initial STM32MP15x SoC diversity introduced by commit 0eda69b6c5f9 ("ARM: dts: stm32: Manage security diversity for STM32M15x SOCs"). Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250603-stm32mp157f-dk2-v2-1-5be0854a9299@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkxOlivier Moysan
The commit 5725bce709db ("ASoC: simple-card-utils: Unify clock direction by clk_direction") corrupts the audio on STM32MP15 DK sound cards. The parent clock is not correctly set, because set_sai_ck_rate() is not executed in stm32_sai_set_sysclk() callback. This occurs because set_sysclk() is called with the wrong direction, SND_SOC_CLOCK_IN instead of SND_SOC_CLOCK_OUT. Add system-clock-direction-out property in SAI2A endpoint node of STM32MP15XX-DKX device tree, to specify the MCLK clock direction. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://lore.kernel.org/r/20250521150418.488152-1-olivier.moysan@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addressesUwe Kleine-König
The efuse device tree description already has the two labels pointing to the efuse nodes that specify the mac-addresses to be used. Wire them up to the ethernet nodes. This is enough to make barebox pick the right mac-addresses and pass them to Linux. Suggested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20250328171406.3307778-2-u.kleine-koenig@baylibre.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04ARM: dts: aspeed: yosemite4: add gpio name for uart mux selMarshall Zhan
Add gpio line name to support multiplexed console Signed-off-by: Marshall Zhan <marshall_zhan@wiwynn.com> Link: https://patch.msgid.link/20250630073138.3315947-1-marshall_zhan@wiwynn.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMCFred Chen
Add linux device tree entry related to the Meta (Facebook) compute node system using an AST2600 BMC. This node is named "Santabarbara". It is a compute node with accelerator module. The system monitors voltage and temperature for the CPU, switch, and NIC components on the motherboard and switch board. Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com> Link: https://patch.msgid.link/20250625073847.4054971-3-fredchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: bletchley: enable USB PD negotiationCosmo Chou
- Enable USB Power Delivery with revision 2.0 for all sleds - Configure dual power/data roles with sink preference Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Link: https://patch.msgid.link/20250622034247.3985727-1-chou.cosmo@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodesAnkit Chauhan
Fix an obvious spelling error in the DTS file for the Lanyang BMC ("lable" -> "label"). This was reported by bugzilla a few years ago but never got fixed. Reported-by: Jens Schleusener <Jens.Schleusener@fossies.org> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=205891 Signed-off-by: Ankit Chauhan <ankitchauhan2065@gmail.com> Link: https://patch.msgid.link/20250612075057.80433-1-ankitchauhan2065@gmail.com [arj: Replace U+2192 with '->'] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add mmc healthPeter Yin
Add a GPIO expander node at address 0x13 on i2c11 bus to monitor MMC health status via a dedicated GPIO line. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-6-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: Harma: revise gpio bride pin for batteryPeter Yin
Update the GPIO bridge pin configuration for the battery circuit on the Harma platform to reflect the correct hardware design. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-5-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoringPeter Yin
Add the ADC128D818 device to I2C bus 29 to support voltage monitoring on the Harma platform. This enables accurate measurement of system voltages through the onboard ADC. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-4-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add fan board I/O expanderPeter Yin
Add GPIO I/O expander node for the fan board to detect and monitor fan board status. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-3-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: harma: add E1.S power monitorPeter Yin
Add the E1.S power monitor device node to the Harma device tree to enable power monitoring functionality for E1.S drives. Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com> Link: https://patch.msgid.link/20250611080514.3123335-2-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-04ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC managementPotin Lai
Add the `mctp-controller` property and MCTP nodes to enable support for frontend NIC management via PLDM over MCTP. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250611-catalina-mctp-i2c-10-15-v1-1-2a882e461ed9@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the documentation. Fix the name in the driver, header and device-tree. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-By: Icenowy Zheng <uwu@icenowy.me> Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-03ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMsUwe Kleine-König
If these PWMs are to be used, a #pwm-cells property is necessary. The right location for that is in the SoC's dtsi file to not make machine.dts files repeat the value for each usage. Currently the machines based on nxp/lpc/lpc32xx.dtsi don't make use of the PWMs, so there are no properties to drop there. Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-03Merge tag 'arm-soc/for-6.17/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree updates for 6.17, please pull the following: - Linus makes a number of updates to the BCMBCA SoCs Device Tree files to correct UART interrupt numbers, add interrupts to the RNG block, and leverage the fact that all SoCs have the same peripherals at the same aperture - Uwe corrects the Merakia MX6X DTS file to have #pwm-cells = 3 as per the binding * tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3> ARM: dts: bcm63178: Add BCMBCA peripherals ARM: dts: bcm63148: Add BCMBCA peripherals ARM: dts: bcm63138: Add BCMBCA peripherals ARM: dts: bcm6878: Add BCMBCA peripherals ARM: dts: bcm6855: Add BCMBCA peripherals ARM: dts: bcm6846: Add interrupt to RNG dt-bindings: rng: r200: Add interrupt property ARM: dts: bcm6878: Correct UART0 IRQ number Link: https://lore.kernel.org/r/20250630190216.1518354-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-02ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definitionPaul Kocialkowski
The V3 supports RGB666 LCD output on PD pins, which are not available on the V3s package. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-2-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definitionPaul Kocialkowski
The V3s (and other packages) supports RGB666 LCD output on PE pins. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-1-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA GTW boardDario Binacchi
Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA RMM boardDario Binacchi
Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA BMM boardDario Binacchi
Support Engicam MicroGEA BMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoMDario Binacchi
Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01ARM: dts: mxs: support i.MX28 Amarula rmm boardDario Binacchi
The board includes the following resources: - 256 Mbytes NAND Flash - 128 Mbytes DRAM DDR2 - CAN - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01ARM: dts: imx28: add pwm7 muxing optionsDario Binacchi
Add alternative pinmuxing for pwm7. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm: dts: omap: Add support for BeagleBone Green Eco boardKory Maincent
SeeedStudio BeagleBone Green Eco (BBGE) is a clone of the BeagleBone Green (BBG). It has minor differences from the BBG, such as a different PMIC, a different Ethernet PHY, and a larger eMMC. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Tested-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250620-bbg-v5-3-84f9b9a2e3a8@bootlin.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-30arm: dts: omap: am335x-bone-common: Rename tps to generic pmic nodeKory Maincent
Rename tps@24 to the generic pmic@24 node name. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Tested-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250620-bbg-v5-1-84f9b9a2e3a8@bootlin.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-27ARM: dts: Fix up wrv54g device treeLinus Walleij
Fix up the KS8995 switch and PHYs the way that is most likely: - Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in the outoftree code masks PHYs 1,2,3,4). - Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly connected to EthC. - The EthB MII is probably connected as CPU interface to the KS8995. Properly integrate the KS8995 switch using the new bindings. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-06-25ARM: dts: microchip: sam9x7: Add LVDS controllerDharma Balasubiramani
Add support for LVDS controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250625-b4-sam9x7-dts-v1-1-92aaee14ed16@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-25ARM: dts: s5pv210: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: s5pv210-fascinate4g.dtb: i2c-gpio-0 (i2c-gpio): $nodename:0: 'i2c-gpio-0' does not match '^i2c(@.+|-[a-z0-9]+)?$' s5pv210-fascinate4g.dtb: i2c-gpio-0 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'audio-codec@1a' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (3 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612094807.62532-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-25ARM: dts: exynos: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: exynos4212-tab3-lte8.dtb: i2c-gpio-3 (i2c-gpio): $nodename:0: 'i2c-gpio-3' does not match '^i2c(@.+|-[a-z0-9]+)?$' exynos4212-tab3-lte8.dtb: i2c-gpio-3 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'magnetometer@2e' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (Exynos3250: 8 controllers, Exynos4: 9 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612094807.62532-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-24ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 46a8a137d8f6 ("ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-4-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 417e58ea41ab ("ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-3-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 09ce8651229b ("ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-2-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 2c0a1faa4da5 ("ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20250521054309.361894-1-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-23Revert "ARM: dts: Update pcie ranges for dra7"Frank Li
This reverts commit c761028ef5e27f477fe14d2b134164c584fc21ee. The commit being reverted updated the "ranges" property for the sake of readability. However, this change is no longer appropriate due to the following reasons: - On many SoCs, the PCIe parent bus translates CPU addresses to different values before passing them to the PCIe controller. - The reverted commit introduced a fake address translation, which violates the fundamental DTS principle: the device tree should reflect actual hardware behavior. Reverting this change prepares for the cleanup of the driver's cpu_addr_fixup() hook. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250411153454.3258098-1-Frank.Li@nxp.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-23ARM: dts: omap: am335x: Use non-deprecated rts-gpiosKrzysztof Kozlowski
The 'rts-gpio' (without trailing 's') is deprecated in favor of 'rts-gpios'. Kernel supports both variants, so switch the DTS to preferred one. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250514125158.56285-2-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-22ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatibleFabio Estevam
The at91-sama5d27_wlsom1 SoM has a WIL3000 Wifi SDIO device populated. Improve the description of the Wifi compatible string by passing the more specific "microchip,wilc3000" string. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250617140502.1042812-1-festevam@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: gardena-smart-gateway: Fix power LEDEzra Buehler
When starting up, the GARDENA smart Gateway's power LED should be flashing green. It is unclear why this has not been done earlier. The LED frequency cannot be configured in the devicetree. Luckily, the default is 1 Hz, which is what we want. Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Link: https://lore.kernel.org/r/20250612074737.311346-1-ezra@easyb.ch Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 41af45af8bc3 ("ARM: dts: at91: sam9x7: add device tree for SoC") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 261dcfad1b59 ("ARM: dts: microchip: add sama7d65 SoC DT") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/3878ae6d0016d46f0c91bd379146d575d5d336aa.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7g5: Adjust clock xtal phandleRyan Wanner
Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add HLCD controllerDharma Balasubiramani
Add support for HLCD controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250611-sam9x7-dts-v1-1-7f52fcb488ad@microchip.com [claudiu.beznea: keep reg the 1st property on port@0 to comply with dts coding style] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Enable CAN busRyan Wanner
Enable CAN bus for SAMA7D65 curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/ab719861de53432bdf19593fa4eee40adf57aed9.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Clean up extra spaceRyan Wanner
Remove the extra space that causes formatting issues. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/ac1decc35e2b4f706cf6ab9378f2c88e5295dde4.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add CAN bus supportRyan Wanner
Add support for CAN bus to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add PWM supportRyan Wanner
Add support for PWMs to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/195c69a19be1ff14736db402e0f1ee64438b4b20.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
generated by cgit v1.2.3 (git 2.51.0) at 2026-10-18 10:33:18 +0000