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2025-11-11drm/amd/display: Refactor HDCP Status Log FormatWenjing Liu
Add missing part for drm/amd/display: fw locality check refactors Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: dynamically clock gate before and after prefetchLeo Chen
[Why] An invalidation request arriving during prefetch can potentially hang the system if dynamic clock gating is enabled and memory power requests are disabled. [How] • Disable clock gating and enable memory power requests for the duration of the prefetch. • Turn on clock gating and disable memory power requests again after prefetch is complete. Limit the scope for DCN35 and DCN42 only. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Revert in_transfer_func_change to MEDDominik Kaszewski
[Why] Last commit accidentally changed handling of in_transfer_func_change from MED to FAST. [How] * Revert the line. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: To support Replay frame skip modeChuntao Tso
[Why & How] The change is to optimize the Replay power saving by reducing the refresh rate with frame skipping mode Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Chuntao Tso <chunttso@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Change lock descriptor valuesDominik Kaszewski
[Why] Review of usage scenarios requires dc_lock_descriptor modification. [How] Replace STATE/LINK/STREAM/PLANE with GLOBAL/STREAM/LINK, where the first means all streams to be locked. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: refactor DSC cap calculation for dcn35Mohit Bawa
why: dcn35 currently uses a hardcoded DSC display clock value which is incorrect for some asic types. Newer DCN versions retrieve dsc display clock from clk_mgr. The same can be done for dcn35. how: Refactor the DSC cap calculation using pre-existing logic. Handle ODM combine requirements in dc_dsc.c. Replace hardcoded display clock with actual value retrieved from clk_mgr. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Mohit Bawa <Mohit.Bawa@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Add new SMART POWER OLED interfacesIan Chen
[why && how] To optimize power consumption on certain OLED LED panels by sending MaxCLL per frame to TCON Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Add interface to capture power feature status for debug loggingGeorge Shen
[Why] The status of various power features is often important information when debugging certain issues, such as underflow. This info helps to narrow down the potential sources of errors. [How] Add dc interface to capture power feature enablement status. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Allow VRR params change if unsynced with the streamIvan Lipski
[Why] When changing resolution (e.g., 4K → FHD) in mirror/clone mode with certain monitors, the monitor blanks and loses connection due to an early exit in vrr_settings_require_update(). The function only checks if VRR state, fixed refresh target, or min/max refresh rate range has changed. During mode changes, if the calculated min/max refresh values remain the same even though the stream's v_total changed, the function returns early without updating vrr_params.adjust.v_total_min/max, leaving the monitor's VRR timing parameters unsynced with the new mode, causing it to blank out. [How] Explicitly adjust VRR parameters to the stream's nominal v_total when VRR is supported, but inactive. Fixes: 6d31602a9f57 ("drm/amd/display: more liberal vmin/vmax update for freesync") Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Fix index bug for fill latencyDillon Varone
[WHY&HOW] This array should be indexed by pstate type followed by plane index. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: Only initialize LSDMA if it is supported in DMUAlvin Lee
Need to check caps flag to determine whether LSDMA is supported in DMU Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/pm: remove unnecessary prints for smu busyGangliang Xie
smu busy is a normal case when calling SMU_MSG_GetBadPageCount, so no need to print error status at each time.Instead, only print error status when timeout given by user is reached. Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: optimize timeout implemention in ras_eeprom_update_record_numTao Zhou
The busy status returned by ras_eeprom_update_record_num may not be an error, increase timeout to exclude false busy status. Also add more comments to make the code readable. v2: define a macro for the timeout value. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: add RAS bad page threshold handling for PMFW manages eepromTao Zhou
Check if bad page threshold is reached and take actions accordingly. v2: remove rma message sent to smu when pmfw manages eeprom. v3: add null pointer check for con. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: fix lock warning in amdgpu_userq_fence_driver_processJesse.Zhang
Fix a potential deadlock caused by inconsistent spinlock usage between interrupt and process contexts in the userq fence driver. The issue occurs when amdgpu_userq_fence_driver_process() is called from both: - Interrupt context: gfx_v11_0_eop_irq() -> amdgpu_userq_fence_driver_process() - Process context: amdgpu_eviction_fence_suspend_worker() -> amdgpu_userq_fence_driver_force_completion() -> amdgpu_userq_fence_driver_process() In interrupt context, the spinlock was acquired without disabling interrupts, leaving it in {IN-HARDIRQ-W} state. When the same lock is acquired in process context, the kernel detects inconsistent locking since the process context acquisition would enable interrupts while holding a lock previously acquired in interrupt context. Kernel log shows: [ 4039.310790] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. [ 4039.310804] kworker/7:2/409 [HC0[0]:SC0[0]:HE1:SE1] takes: [ 4039.310818] ffff9284e1bed000 (&fence_drv->fence_list_lock){?...}-{3:3}, [ 4039.310993] {IN-HARDIRQ-W} state was registered at: [ 4039.311004] lock_acquire+0xc6/0x300 [ 4039.311018] _raw_spin_lock+0x39/0x80 [ 4039.311031] amdgpu_userq_fence_driver_process.part.0+0x30/0x180 [amdgpu] [ 4039.311146] amdgpu_userq_fence_driver_process+0x17/0x30 [amdgpu] [ 4039.311257] gfx_v11_0_eop_irq+0x132/0x170 [amdgpu] Fix by using spin_lock_irqsave()/spin_unlock_irqrestore() to properly manage interrupt state regardless of calling context. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: try for more times if RAS bad page number is not updatedTao Zhou
RAS info update in PMFW is time cost, wait for it. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: jump to the correct label on failurePierre-Eric Pelloux-Prayer
drm_sched_entity_init wasn't called yet, so the only thing to do is to release allocated memory. This doesn't fix any bug since entity is zero allocated and drm_sched_entity_fini does nothing in this case. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdkfd: Fixing the clang formatAhmad Rehman
This patch fixes the formatting in the patch "amdkfd: Do not wait for queue op response during reset" Signed-off-by: Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/pm: Add NULL check for power limitAsad Kamal
Add NULL check for smu power limit pointer v2: Update error code on failure (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: get RAS bad page address from MCA addressTao Zhou
Instead of from physical address. v2: add comment to make the code more readable Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd: Clarify that amdgpu.audio only works for non-DCMario Limonciello (AMD)
The comment already explains it but the module parameter help text doesn't. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4684 Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: disable peer-to-peer access for DCC-enabled GC12 VRAM surfacesVitaly Prosyak
Certain multi-GPU configurations (especially GFX12) may hit data corruption when a DCC-compressed VRAM surface is shared across GPUs using peer-to-peer (P2P) DMA transfers. Such surfaces rely on device-local metadata and cannot be safely accessed through a remote GPU’s page tables. Attempting to import a DCC-enabled surface through P2P leads to incorrect rendering or GPU faults. This change disables P2P for DCC-enabled VRAM buffers that are contiguous and allocated on GFX12+ hardware. In these cases, the importer falls back to the standard system-memory path, avoiding invalid access to compressed surfaces. Future work could consider optional migration (VRAM→System→VRAM) if a performance regression is observed when `attach->peer2peer = false`. Tested on: - Dual RX 9700 XT (Navi4x) setup - GNOME and Wayland compositor scenarios - Confirmed no corruption after disabling P2P under these conditions v2: Remove check TTM_PL_VRAM & TTM_PL_FLAG_CONTIGUOUS. v3: simplify for upsteam and fix ip version check (Alex) Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amd/display: add macros to simplify codeWenjing Liu
[Why & How] Adding macros to simplify the process of adding new error codes. Currently, to add an error code, the developer needs to add both the enum and the string translation. This is error prone and can lead to inconsistencies. The refactor adds a macro to automatically add the string translation based on the enum. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu: load RAS bad page from PMFW in page retirementTao Zhou
In legacy way, bad page is queried from MCA registers, switch to getting it from PMFW when PMFW manages eeprom data. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11net: sparx5/lan969x: populate netdev of_nodeRobert Marko
Populate of_node for the port netdevs, to make the individual ports of_nodes available in sysfs. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://patch.msgid.link/20251110124342.199216-1-robert.marko@sartura.hr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-12arm64: dts: imx95-19x19-evk: Add vpcie3v3aux regulator for PCIe[0,1]Richard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector(PCIe0) on i.MX95 19x19 EVK board. PCIe1 uses one standard PCIe slot connector, but combines the +3.3v and +3.3Vaux into a same 3.3v power source, and intends to let it always on. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe1 on i.MX95 19x19 EVK board too. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx95-15x15-evk: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX95 15x15 EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8qxp-mek: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX8QXP MEK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8qm-mek: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX8QM MEK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8mq-evk: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX8MQ EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8mp-evk: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX8MP EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8dxl-evk: Add vpcie3v3aux regulator for PCIe M.2 connectorRichard Zhu
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and Grounds. PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage source, 3.3 V, is expected to be available during the system’s stand-by/suspend state to support wake event processing on the communications card. Add vpcie3v3aux regulator to let this 3.3 V power source always on for PCIe M.2 Key E connector on i.MX8DXL EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-11net_sched: limit try_bulk_dequeue_skb() batchesEric Dumazet
After commit 100dfa74cad9 ("inet: dev_queue_xmit() llist adoption") I started seeing many qdisc requeues on IDPF under high TX workload. $ tc -s qd sh dev eth1 handle 1: ; sleep 1; tc -s qd sh dev eth1 handle 1: qdisc mq 1: root Sent 43534617319319 bytes 268186451819 pkt (dropped 0, overlimits 0 requeues 3532840114) backlog 1056Kb 6675p requeues 3532840114 qdisc mq 1: root Sent 43554665866695 bytes 268309964788 pkt (dropped 0, overlimits 0 requeues 3537737653) backlog 781164b 4822p requeues 3537737653 This is caused by try_bulk_dequeue_skb() being only limited by BQL budget. perf record -C120-239 -e qdisc:qdisc_dequeue sleep 1 ; perf script ... netperf 75332 [146] 2711.138269: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1292 skbaddr=0xff378005a1e9f200 netperf 75332 [146] 2711.138953: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1213 skbaddr=0xff378004d607a500 netperf 75330 [144] 2711.139631: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1233 skbaddr=0xff3780046be20100 netperf 75333 [147] 2711.140356: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1093 skbaddr=0xff37800514845b00 netperf 75337 [151] 2711.141037: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1353 skbaddr=0xff37800460753300 netperf 75337 [151] 2711.141877: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1367 skbaddr=0xff378004e72c7b00 netperf 75330 [144] 2711.142643: qdisc:qdisc_dequeue: dequeue ifindex=5 qdisc handle=0x80150000 parent=0x10013 txq_state=0x0 packets=1202 skbaddr=0xff3780045bd60000 ... This is bad because : 1) Large batches hold one victim cpu for a very long time. 2) Driver often hit their own TX ring limit (all slots are used). 3) We call dev_requeue_skb() 4) Requeues are using a FIFO (q->gso_skb), breaking qdisc ability to implement FQ or priority scheduling. 5) dequeue_skb() gets packets from q->gso_skb one skb at a time with no xmit_more support. This is causing many spinlock games between the qdisc and the device driver. Requeues were supposed to be very rare, lets keep them this way. Limit batch sizes to /proc/sys/net/core/dev_weight (default 64) as __qdisc_run() was designed to use. Fixes: 5772e9a3463b ("qdisc: bulk dequeue support for qdiscs with TCQ_F_ONETXQUEUE") Signed-off-by: Eric Dumazet <edumazet@google.com> Reviewed-by: Toke Høiland-Jørgensen <toke@redhat.com> Acked-by: Jesper Dangaard Brouer <hawk@kernel.org> Link: https://patch.msgid.link/20251109161215.2574081-1-edumazet@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11Merge branch 'net-stmmac-convert-meson8b-to-use-stmmac_get_phy_intf_sel'Jakub Kicinski
Russell King says: ==================== net: stmmac: convert meson8b to use stmmac_get_phy_intf_sel() This series splits out meson8b from the previous 16 patch series as that now has r-b tags. This series converts meson8b to use stmmac_get_phy_intf_sel(). This driver is not converted to the set_phy_intf_sel() method as it is unclear whether there are ordering dependencies that would prevent it. I would appreciate the driver author looking in to whether this conversion is possible. ==================== Link: https://patch.msgid.link/aRH50uVDX4_9O5ZU@shell.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11net: stmmac: meson8b: use stmmac_get_phy_intf_sel()Russell King (Oracle)
Use stmmac_get_phy_intf_sel() to decode the PHY interface mode to the phy_intf_sel value, validate the result and use that to set the control register to select the operating mode for the DWMAC core. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vIT6b-0000000DpPX-1LQ0@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11net: stmmac: meson8b: use phy_intf_sel directlyRussell King (Oracle)
Rearrange meson_axg_set_phy_mode() to use phy_intf_sel directly, converting it to the register field for meson8b_dwmac_mask_bits(). Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vIT6W-0000000DpPR-0tby@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11net: stmmac: meson8b: use PHY_INTF_SEL_xRussell King (Oracle)
Use PHY_INTF_SEL_x definitions for phy_intf_sel bitfield. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vIT6R-0000000DpPL-0Nli@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11MAINTAINERS: Add Magnus Lindholm as maintainer for alpha portMagnus Lindholm
Acked-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Acked-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Signed-off-by: Matt Turner <mattst88@gmail.com>
2025-11-12arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8qxp-mek matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8qm-mek: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8qm-mek matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8mq-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8mp-evk: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8mp-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx8mm-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx95-19x19-evk: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx95-19x19-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-12arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 portRichard Zhu
According to PCIe r6.1, sec 5.5.1. The following rules define how the L1.1 and L1.2 substates are entered: Both the Upstream and Downstream Ports must monitor the logical state of the CLKREQ# signal. Typical implement is using open drain, which connect RC's clkreq# to EP's clkreq# together and pull up clkreq#. imx95-15x15-evk matches this requirement, so add supports-clkreq to allow PCIe device enter ASPM L1 Sub-State. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-11-11Merge branch 'selftests-mptcp-join-fix-some-flaky-tests'Jakub Kicinski
Matthieu Baerts says: ==================== selftests: mptcp: join: fix some flaky tests When looking at the recent CI results on NIPA and MPTCP CIs, a few MPTCP Join tests are marked as unstable. Here are some fixes for that. - Patch 1: a small fix for mptcp_connect.sh, printing a note as initially intended. For >=v5.13. - Patch 2: avoid unexpected reset when closing subflows. For >= 5.13. - Patches 3-4: longer transfer when not waiting for the end. For >=5.18. - Patch 5: read all received data when expecting a reset. For >= v6.1. - Patch 6: a fix to properly kill background tasks. For >= v6.5. ==================== Link: https://patch.msgid.link/20251110-net-mptcp-sft-join-unstable-v1-0-a4332c714e10@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11selftests: mptcp: join: properly kill background tasksMatthieu Baerts (NGI0)
The 'run_tests' function is executed in the background, but killing its associated PID would not kill the children tasks running in the background. To properly kill all background tasks, 'kill -- -PID' could be used, but this requires kill from procps-ng. Instead, all children tasks are listed using 'ps', and 'kill' is called with all PIDs of this group. Fixes: 31ee4ad86afd ("selftests: mptcp: join: stop transfer when check is done (part 1)") Cc: stable@vger.kernel.org Fixes: 04b57c9e096a ("selftests: mptcp: join: stop transfer when check is done (part 2)") Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org> Link: https://patch.msgid.link/20251110-net-mptcp-sft-join-unstable-v1-6-a4332c714e10@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11selftests: mptcp: connect: trunc: read all recv dataMatthieu Baerts (NGI0)
MPTCP Join "fastclose server" selftest is sometimes failing because the client output file doesn't have the expected size, e.g. 296B instead of 1024B. When looking at a packet trace when this happens, the server sent the expected 1024B in two parts -- 100B, then 924B -- then the MP_FASTCLOSE. It is then strange to see the client only receiving 296B, which would mean it only got a part of the second packet. The problem is then not on the networking side, but rather on the data reception side. When mptcp_connect is launched with '-f -1', it means the connection might stop before having sent everything, because a reset has been received. When this happens, the program was directly stopped. But it is also possible there are still some data to read, simply because the previous 'read' step was done with a buffer smaller than the pending data, see do_rnd_read(). In this case, it is important to read what's left in the kernel buffers before stopping without error like before. SIGPIPE is now ignored, not to quit the app before having read everything. Fixes: 6bf41020b72b ("selftests: mptcp: update and extend fastclose test-cases") Cc: stable@vger.kernel.org Reviewed-by: Geliang Tang <geliang@kernel.org> Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org> Link: https://patch.msgid.link/20251110-net-mptcp-sft-join-unstable-v1-5-a4332c714e10@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11selftests: mptcp: join: userspace: longer transferMatthieu Baerts (NGI0)
In rare cases, when the test environment is very slow, some userspace tests can fail because some expected events have not been seen. Because the tests are expecting a long on-going connection, and they are not waiting for the end of the transfer, it is fine to make the connection longer. This connection will be killed at the end, after the verifications, so making it longer doesn't change anything, apart from avoid it to end before the end of the verifications To play it safe, all userspace tests not waiting for the end of the transfer are now sharing a longer file (128KB) at slow speed. Fixes: 4369c198e599 ("selftests: mptcp: test userspace pm out of transfer") Cc: stable@vger.kernel.org Fixes: b2e2248f365a ("selftests: mptcp: userspace pm create id 0 subflow") Fixes: e3b47e460b4b ("selftests: mptcp: userspace pm remove initial subflow") Fixes: b9fb176081fb ("selftests: mptcp: userspace pm send RM_ADDR for ID 0") Reviewed-by: Geliang Tang <geliang@kernel.org> Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org> Link: https://patch.msgid.link/20251110-net-mptcp-sft-join-unstable-v1-4-a4332c714e10@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-11-11selftests: mptcp: join: endpoints: longer transferMatthieu Baerts (NGI0)
In rare cases, when the test environment is very slow, some userspace tests can fail because some expected events have not been seen. Because the tests are expecting a long on-going connection, and they are not waiting for the end of the transfer, it is fine to make the connection longer. This connection will be killed at the end, after the verifications, so making it longer doesn't change anything, apart from avoid it to end before the end of the verifications To play it safe, all endpoints tests not waiting for the end of the transfer are now sharing a longer file (128KB) at slow speed. Fixes: 69c6ce7b6eca ("selftests: mptcp: add implicit endpoint test case") Cc: stable@vger.kernel.org Fixes: e274f7154008 ("selftests: mptcp: add subflow limits test-cases") Fixes: b5e2fb832f48 ("selftests: mptcp: add explicit test case for remove/readd") Fixes: e06959e9eebd ("selftests: mptcp: join: test for flush/re-add endpoints") Reviewed-by: Geliang Tang <geliang@kernel.org> Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org> Link: https://patch.msgid.link/20251110-net-mptcp-sft-join-unstable-v1-3-a4332c714e10@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>