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2025-12-30arm64: dts: imx93-11x11-evk: Use phys to replace xceiver-supplyPeng Fan
The TJA1057 used on i.MX93 EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8mp-evk: Use phys to replace xceiver-supplyPeng Fan
The TJA1048 used on i.MX8MP-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx95-15x15-evk: Use phys to replace xceiver-supplyPeng Fan
The TJA1051T/3 used on i.MX95-15x15-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30ARM: dts: imx6qdl: Add default GIC address cellsAlexander Stein
Add missing address-cells 0 to GPC interrupt node to silence W=1 warning: imx6qdl.dtsi:281.4-284.29: Warning (interrupt_map): /soc/pcie@1ffc000:interrupt-map: Missing property '#address-cells' in node /soc/bus@2000000/gpc@20dc000, using 0 as fallback Value '0' is correct because: 1. GPC interrupt controller children are only power domains, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30dt-bindings: power: fsl,imx-gpc: Document address-cellsAlexander Stein
The GPC power controller is an interrupt controllers and can be referenced in interrupt-map properties, e.g. PCIe controller, thus the node should have address-cells property. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30drm/i915/vrr: Enable DC BalanceMitul Golani
Enable DC Balance from vrr compute config and related hw flag. Also to add pipe restrictions along with this. --v2: - Use dc balance check instead of source restriction. --v3: - Club pipe restriction check with dc balance enablement. (Ankit) --v4: - Separate out Pipe restrictions to patch#7 Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-19-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add function to configure event for dc balanceMitul Golani
Configure pipe dmc event for dc balance enable/disable. --v2: - Keeping function and removing unnecessary comments. (Jani, Nikula) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-18-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Pause DC Balancing for DSB commitsVille Syrjälä
Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands. --v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. --v4: - Move events to separate function. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/dsb: Add pipedmc dc balance enable/disableVille Syrjälä
Add function to control DC balance enable/disable bit via DSB. --v2: Remove redundant forward declaration. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-16-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Wait for VRR PUSH status updateMitul Golani
After VRR Push is sent, need to wait till flipline decision boundary to get Push bit to get cleared. --v2: - Adjust delays to vrr vmin vblank delays. (Ankit) --v3: - Change intel_vrr_vmin_safe_window_end() so that intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit) --v4: - Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-15-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Implement vblank evasion with DC balancingVille Syrjälä
Add vblank evasion logic when vrr is already enabled along with dc balance is computed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-14-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vblank: Extract vrr_vblank_start()Ville Syrjälä
Initialise delayed vblank position for evasion logic. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-13-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Write DC balance params to hw registersMitul Golani
Write DC Balance parameters to hw registers. --v2: - Update commit header. - Separate crtc_state params from this patch. (Ankit) --v3: - Write registers at compute config. - Update condition for write. --v4: - Address issue with state checker. --v5: - Initialise some more dc balance register while enabling VRR. --v6: - FLIPLINE_CFG need to be configure at last, as it is double buffer arming point. --v7: - Initialise and reset live value of vmax and vmin as well. --v8: - Add separate functions while writing hw registers. (Ankit) --v9: - Add DC Balance counter enable bit to this patch. (Ankit) --v10: - Add rigister writes to vrr_enable/disable. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-12-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add DC Balance flip count operationsMitul Golani
Track dc balance flip count with params per crtc. Increment DC Balance Flip count before every flip to indicate DMC firmware about new flip occurrence which needs to be adjusted for dc balancing. This is tracked separately from legacy FLIP_COUNT register also Reset DC balance flip count value while disabling VRR adaptive mode, this is to start with fresh counts when VRR adaptive refresh mode is triggered again. --v2: - Call during intel_update_crtc.(Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-11-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add function to reset DC balance accumulated paramsMitul Golani
Add function which resets all accumulated DC Balance parameters whenever adaptive mode of VRR goes off. This helps to give a fresh start when VRR is re-enabled. --v2: - Typo, change crtc_state to old_crtc_state. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-10-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add function to check if DC Balance PossibleMitul Golani
Add a function that checks if DC Balance enabling is possible on the requested PIPE. Apart from the DISPLAY_VER check, account for current firmware limitations, which only allow DC Balance on PIPE A and PIPE B. v2: Rephrased commit message. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-9-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add compute config for DC Balance paramsMitul Golani
Compute DC Balance parameters and tunable params based on experiments. --v2: - Document tunable params. (Ankit) --v3: - Add line spaces to compute config. (Ankit) - Remove redundancy checks. --v4: - Separate out conpute config to separate function. - As all the valuse are being computed in scanlines, and slope is still in usec, convert and store it to scanlines. --v5: - Update and add comments for slope calculation. (Ankit) - Update early return conditions for dc balance compute. (Ankit) --v6: - Early return condition simplified for dc balance compute config. (Ankit) - Make use of pipe restrictions to this patch. (Ankit) --v7: - Separate out PIPE_A and PIPE_B restrictions to other patch.(Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-8-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add state dump for DC Balance paramsMitul Golani
Add state dump for dc balance params to track DC Balance crtc state config. -v1: -- nitpick: s/Vblank target/vblank target. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-7-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add DC Balance params to crtc_stateMitul Golani
Add DC Balance params to crtc_state, also add state checker params for related properties. --v3: - Seggregate crtc_state params with this patch. (Ankit) --v4: - Update commit message and header. (Ankit) - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit) --v5: - Add headers in sorted order. (Jani Nikula) --v6: - Add a separate function to get and check dc_balance params. - Avoid repeatative use of MMIO read. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-6-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add functions to read out vmin/vmax stuffVille Syrjälä
Calculate delayed vblank start position with the help of added vmin/vmax stuff for next frame and final computation. --v2: - Correct Author details. --v3: - Separate register details from this patch. --v4: - Add mask macros. --v5: - As live prefix params indicate timings for current frame, read just _live prefix values instead of next frame timings as done previously. - Squash Refactor vrr params patch. --v6: - Use error code while returning invalid values. (Jani, Nikula) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-5-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add VRR DC balance registersMitul Golani
Add VRR register offsets and bits to access DC Balance configuration. --v2: - Separate register definitions. (Ankit) - Remove usage of dev_priv. (Jani, Nikula) --v3: - Convert register address offset, from capital to small. (Ankit) - Move mask bits near to register offsets. (Ankit) --v4: - Use _MMIO_TRANS wherever possible. (Jani) --v5: - Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw - For pipe B it is temporary and expected to change later once finalised. --v6: - Add live value registers for DCB VMAX/FLIPLINE. --v7: - Correct commit message file. (Jani Nikula) - Add bits in highest to lowest order. (Jani Nikula) --v8: - Register/bitfields indentation changes as per i915_reg.h mentioned format (Jani, Ankit) --v9: - Remove comment. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-4-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/dmc: Add pipe dmc registers and bits for DC BalanceVille Syrjälä
Add pipe dmc registers and access bits for DC Balance params configuration and enablement. --v2: - Separate register definitions for transcoder and pipe dmc. (Ankit) - Use MMIO pipe macros instead of transcoder ones. (Ankit) - Remove dev_priv use. (Jani, Nikula) --v3: - Add all register address, from capital alphabet to small. (Ankit) - Add EVT CTL registers. - Add co-author tag. - Add event flag for Triggering DC Balance. --v4: - Add DCB Flip count and balance reset registers. --v5: - Correct macro usage for flip count. (Ankit) - Use register offset in lower case. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-3-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add source param for dc balanceMitul Golani
Add source param for dc balance enablement. --v2: - Arrange in alphabetic order. (Ankit) - Update name. (Ankit) --v3: - Commit message update. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-2-mitulkumar.ajitkumar.golani@intel.com
2025-12-30arm64: dts: imx8m{m,p}-venice-gw71xx: Add MagetometerTim Harvey
Add support for the optional LIS2MDL magnetometer on GW71xx baseboards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mp-ras314: Add HDMI audio output supportAlexander Stein
Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mp-ras314: Fix HDMI CEC pad control settingsAlexander Stein
As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: ddabb3ce3f90 ("arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mp-ras314: Fix Ethernet PHY IRQ supportAlexander Stein
Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mpxl: Configure IEEE 1588 event out signalAlexander Stein
The event out signal on channel 2 is available on pad SAI2_RXD0 which is connected to X63 pin 13. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mpxl: Add HDMI audio output supportAlexander Stein
Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mpxl: Fix HDMI CEC pad control settingsAlexander Stein
As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: 418d1d840e42 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mpxl: Fix Ethernet PHY IRQ supportAlexander Stein
Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: tqma8mpql-mba8mpxl: Adjust copyright text formatAlexander Stein
Replace personal mail address by mailing list. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: imx8mp-toradex-smarc: enable hdmi_pai deviceFrancesco Dolcini
Enable the hdmi_pai device on the Toradex SMARC iMX8M Plus Development boards. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: imx8mp-verdin: enable hdmi_pai deviceFrancesco Dolcini
Enable the hdmi_pai device on the various iMX8M Plus Verdin boards that feature the related HDMI interface. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: imx8mp-verdin: Remove obsolete TODO commentsFrancesco Dolcini
Remove obsolete TODO comments, I2S interface is supported since Linux v6.6. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: imx8-apalis: Add ethernet aliasFrancesco Dolcini
Add alias for the apalis first ethernet interface, this ensures consistent interface naming (e.g. `end0`) and this is used by the firmware to correctly set the MAC address. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx93-var-som-symphony: Enable LPSPI6 controllerStefano Radaelli
Enable the LPSPI6 controller so it can be used by user applications through the board’s expansion connector. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx93-var-som-symphony: Add USB supportStefano Radaelli
The Symphony carrier board includes a USB Type-C connector on the USB1 port through an NXP PTN5150 Type-C controller connected on the I2C bus. The PTN5150 provides cable orientation detection and role switching information to the USB controller. This patch adds the PTN5150 node, its interrupt line, the required pin muxing, and wires the controller to the USB1 OTG dual-role device using the USB role-switch framework. This patch adds also USB2 support, that remains in host-only mode, matching the hardware capabilities of the Symphony board. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controllerStefano Radaelli
The Symphony carrier board exposes a capacitive touch interface through an FFC/FPC connector. This interface is wired to an FT5x06 touch controller on the I2C bus when using Variscite’s 7-inch capacitive touch display. This patch adds the FT5x06 device node to describe the actual hardware connection and enables touch functionality on the Symphony board Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx93-var-som-symphony: Update gpio aliasesStefano Radaelli
This patch introduces 2 simple aliases: Add a gpio3->gpio4 alias to allow flexible access to these GPIOs Add a gpio4 alias for the PCA9534 GPIO expander. Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-05 expansion boardYannic Moog
PEB-WLBT-05 is an expansion board that provides WIFI and Bluetooth functionality. It features the Ezurio Sterling LWB module [1]. Add missing regulator to baseboard dts. [1] https://www.ezurio.com/wireless-modules/wifi-modules-bluetooth/sterling-lwb-24-ghz-wifi-4-bt-51-module Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8mp-phyboard-pollux: Enable i2c3Stefan Riedmueller
The i2c3 of the phyBOARD-Pollux is used on the CSI1 interface to connect to imaging sensors. Thus define it so it can be easily enabled if required. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8mp-phycore-som: add spi-nor supply vccYannic Moog
The spi flash on the SoM is missing its vcc supply definition. Add missing regulator which supplies the flash with 1.8V. Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8mp-phyboard-pollux: add fan-supplyYannic Moog
Add 5v regulator to gpio fan node. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx91-11x11-evk: Add audio XCVR sound card supportChancel Liu
Add audio XCVR sound card, which supports SPDIF TX & RX only, eARC RX, ARC RX are not supported. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx91-11x11-evk: Add PDM microphone sound card supportChancel Liu
Add PDM micphone sound card support. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx91-11x11-evk: Add WM8962 sound card supportChancel Liu
Add WM8962 sound card support which connects to SAI3. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx91-11x11-evk: Add bt-sco sound card supportChancel Liu
Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx91-11x11-evk: Refine label and node name of WM8962Chancel Liu
Refine label with "wm8962" and node name with "codec" to follow devicetree specification. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuartSherry Sun
The commit 616effc0272b5 ("arm64: dts: imx8: Fix lpuart DMA channel order") swap uart rx and tx channel at common imx8-ss-dma.dtsi. But miss update imx8qm-ss-dma.dtsi. The commit 5a8e9b022e569 ("arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names") just simple add dma-names as binding doc requirement. Correct lpuart0 - lpuart3 dma rx and tx channels, and use defines for the FSL_EDMA_RX flag. Fixes: 5a8e9b022e56 ("arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names") Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-09 10:24:42 +0000