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2026-01-09arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keysCosmin Tanislav
The Renesas RZ/T2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add GPIO IRQ supportCosmin Tanislav
The Renesas RZ/N2H (R9A09G087) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add GPIO IRQ supportCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251205150234.2958140-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add TSU and thermal zones supportCosmin Tanislav
The Renesas RZ/N2H (R9A09G087) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-10-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add TSU and thermal zones supportCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g087: Add OPP tableCosmin Tanislav
Add OPP table for RZ/N2H SoC. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: dts: renesas: r9a09g077: Add OPP tableCosmin Tanislav
Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251126130356.2768625-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09arm64: Fix cleared E0POE bit after cpu_suspend()/resume()Yeoreum Yun
TCR2_ELx.E0POE is set during smp_init(). However, this bit is not reprogrammed when the CPU enters suspension and later resumes via cpu_resume(), as __cpu_setup() does not re-enable E0POE and there is no save/restore logic for the TCR2_ELx system register. As a result, the E0POE feature no longer works after cpu_resume(). To address this, save and restore TCR2_EL1 in the cpu_suspend()/cpu_resume() path, rather than adding related logic to __cpu_setup(), taking into account possible future extensions of the TCR2_ELx feature. Fixes: bf83dae90fbc ("arm64: enable the Permission Overlay Extension for EL0") Cc: <stable@vger.kernel.org> # 6.12.x Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2026-01-09x86/CPU/AMD: Simplify the spectral chicken fixBorislav Petkov (AMD)
msr_set_bit() takes a bit number to set but MSR_ZEN2_SPECTRAL_CHICKEN_BIT is a bit mask. The usual pattern that code uses is a _BIT-named type macro instead of a mask. So convert it to a bit number to reflect that. Also, msr_set_bit() already does the reading and checking whether the bit needs to be set so use that instead of a local variable. Fixup tabbing while at it. No functional changes. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Nikolay Borisov <nik.borisov@suse.com> Link: https://patch.msgid.link/20251230110731.28108-1-bp@kernel.org
2026-01-09clk: renesas: rzv2h: Deassert reset on assert timeoutBiju Das
If the assert() fails due to timeout error, set the reset register bit back to deasserted state. This change is needed especially for handling assert error in suspend() callback that expect the device to be in operational state in case of failure. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260108123433.104464-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09clk: renesas: rzg2l: Deassert reset on assert timeoutBiju Das
If the assert() fails due to timeout error, set the reset register bit back to deasserted state. This change is needed especially for handling assert error in suspend() callback that expect the device to be in operational state in case of failure. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260108123433.104464-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09clk: renesas: cpg-mssr: Unlock before reset verificationLad Prabhakar
Move spin_unlock_irqrestore() before verifying the reset result and printing errors. The verification condition only uses local variables and does not require locking. Reported-by: Pavel Machek <pavel@nabladev.com> Closes: https://lore.kernel.org/all/aVujAQJSDn6WyORK@duo.ucw.cz/ Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105140625.2590685-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09clk: renesas: r9a09g056: Add entries for CANFDLad Prabhakar
Add clock and reset entries for the CANFD IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224165049.3384870-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09clk: renesas: r9a09g057: Add entries for CANFDLad Prabhakar
Add clock and reset entries for the CANFD IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224165049.3384870-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09clk: renesas: r9a09g077: Add CANFD clocksLad Prabhakar
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a CANFD peripheral which has three input clocks PCLKM (peripheral clock), PCLKH (RAM clock) and PCLKCAN (CANFD clock). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251224165049.3384870-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09Merge tag 'renesas-r9a09g077-dt-binding-defs-tag6' into renesas-clk-for-v6.20Geert Uytterhoeven
Renesas RZ/T2H and RZ/N2H PCLKCAN Clock DT Binding Definitions PCLKCAN Clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2026-01-09clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacksCosmin Tanislav
The register layout for RZ/T2H is not handled inside cpg_mssr_suspend_noirq() and cpg_mssr_resume_noirq(), causing a memory abort because the wrong code path is taken, as shown below. Explicitly handle the RZ/T2H register layout in cpg_mssr_suspend_noirq() and cpg_mssr_resume_noirq(), similar to how it is done inside cpg_mstp_clock_is_enabled() and cpg_mstp_clock_endisable(). [ 90.052296] Mem abort info: [ 90.055420] ESR = 0x0000000096000007 [ 90.059553] EC = 0x25: DABT (current EL), IL = 32 bits [ 90.065697] SET = 0, FnV = 0 [ 90.069211] EA = 0, S1PTW = 0 [ 90.072834] FSC = 0x07: level 3 translation fault [ 90.078109] Data abort info: [ 90.081405] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000 [ 90.087427] CM = 0, WnR = 0, TnD = 0, TagAccess = 0 [ 90.093169] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0 [ 90.099008] swapper pgtable: 4k pages, 48-bit VAs, pgdp=00000000c60b4000 [ 90.106756] [ffff800082816318] pgd=0000000000000000, p4d=10000000c69ef003, pud=10000000c69f0003, pmd=100000024002b403, pte=0000000000000000 [ 90.120727] Internal error: Oops: 0000000096000007 [#1] SMP [ 90.127058] Modules linked in: sha256 cfg80211 spi_nor at24 renesas_usbhs bluetooth ecdh_generic ecc rfkill rzt2h_adc spi_rzv2h_rspi industrialio_adc gpio_keys fuse drm backlight ipv6 [ 90.145201] CPU: 0 UID: 0 PID: 307 Comm: sh Not tainted 6.18.0-rc1-next-20251016+ #47 PREEMPT [ 90.155006] Hardware name: Renesas RZ/T2H EVK Board based on r9a09g077m44 (DT) [ 90.163041] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 90.170777] pc : cpg_mssr_suspend_noirq+0x4c/0xc0 [ 90.175983] lr : device_suspend_noirq+0x6c/0x22c [ 90.181309] sp : ffff8000838d3af0 [ 90.185026] x29: ffff8000838d3af0 x28: ffff8000825c016f x27: ffff8000825c01a0 [ 90.192973] x26: ffff8000809feeec x25: ffff8000827bebb8 x24: 0000000000000002 [ 90.200815] x23: ffff8000825c0190 x22: 0000000000000002 x21: 0000000000000000 [ 90.209058] x20: ffff8000827bebb8 x19: ffff000180128010 x18: ffff00033ef92a80 [ 90.217100] x17: ffff000180051700 x16: 0000000000000001 x15: ffff000187afc310 [ 90.224847] x14: 0000000000000254 x13: 0000000000000001 x12: 0000000000000001 [ 90.232793] x11: 00000000000000c0 x10: 0000000000000ab0 x9 : ffff8000838d38b0 [ 90.240540] x8 : ffff000186387410 x7 : 0000000000000001 x6 : 0000000000000000 [ 90.248600] x5 : ffff0001803240d4 x4 : 0000000000000003 x3 : ffff0001803240d0 [ 90.256460] x2 : ffff800082816318 x1 : 000000000000000c x0 : ffff000180324000 [ 90.264208] Call trace: [ 90.267019] cpg_mssr_suspend_noirq+0x4c/0xc0 (P) [ 90.272450] device_suspend_noirq+0x6c/0x22c [ 90.277375] dpm_noirq_suspend_devices+0x1a8/0x2a0 [ 90.282902] dpm_suspend_noirq+0x24/0xa0 [ 90.287428] suspend_devices_and_enter+0x310/0x590 [ 90.292790] pm_suspend+0x1b4/0x200 [ 90.296811] state_store+0x80/0xf4 [ 90.300676] kobj_attr_store+0x18/0x34 [ 90.305002] sysfs_kf_write+0x7c/0x94 [ 90.309232] kernfs_fop_write_iter+0x12c/0x200 [ 90.314115] vfs_write+0x240/0x380 [ 90.318041] ksys_write+0x64/0x100 [ 90.321862] __arm64_sys_write+0x18/0x24 [ 90.326013] invoke_syscall.constprop.0+0x40/0xf0 [ 90.331445] el0_svc_common.constprop.0+0xb8/0xd8 [ 90.336554] do_el0_svc+0x1c/0x28 [ 90.340375] el0_svc+0x34/0xe8 [ 90.343900] el0t_64_sync_handler+0xa0/0xe4 [ 90.348426] el0t_64_sync+0x198/0x19c [ 90.352609] Code: 8b040042 b9409004 7100049f 54000240 (b9400042) [ 90.359639] ---[ end trace 0000000000000000 ]--- Fixes: 065fe720eec6 ("clk: renesas: Add support for R9A09G077 SoC") Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251127145654.3253992-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-01-09mm/memtest: add underflow detection for size calculationKevin Lourenco
The computation: end = start + (size - (start_phys_aligned - start_phys)) / incr could theoretically underflow if size < offset, leading to a massive iteration. Add VM_WARN_ON_ONCE() to detect cases where the region size is smaller than the alignment offset. While this should never happen in practice due to memblock guarantees, the warning helps catch potential bugs in early memory initialization code. Suggested-by: Mike Rapoport <rppt@kernel.org> Signed-off-by: Kevin Lourenco <klourencodev@gmail.com> Link: https://patch.msgid.link/20251229161321.9079-1-klourencodev@gmail.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-01-09memblock: drop redundant 'struct page *' argument from memblock_free_pages()Shengming Hu
memblock_free_pages() currently takes both a struct page * and the corresponding PFN. The page pointer is always derived from the PFN at call sites (pfn_to_page(pfn)), making the parameter redundant and also allowing accidental mismatches between the two arguments. Simplify the interface by removing the struct page * argument and deriving the page locally from the PFN, after the deferred struct page initialization check. This keeps the behavior unchanged while making the helper harder to misuse. Signed-off-by: Shengming Hu <hu.shengming@zte.com.cn> Reviewed-by: David Hildenbrand (Red Hat) <david@kernel.org> Link: https://patch.msgid.link/tencent_F741CE6ECC49EE099736685E60C0DBD4A209@qq.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-01-09pinctrl: meson: amlogic-a4: mark the GPIO controller as sleepingBartosz Golaszewski
The GPIO controller is configured as non-sleeping but it uses generic pinctrl helpers which use a mutex for synchronization. This will cause lockdep splats when used together with shared GPIOs going through the GPIO shared proxy driver. Fixes: 6e9be3abb78c ("pinctrl: Add driver support for Amlogic SoCs") Cc: stable@vger.kernel.org Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Closes: https://lore.kernel.org/all/CAFBinCAc7CO8gfNQakCu3LfkYXuyTd2iRpMRm8EKXSL0mwOnJw@mail.gmail.com/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-09can: gs_usb: gs_usb_receive_bulk_callback(): fix URB memory leakMarc Kleine-Budde
In gs_can_open(), the URBs for USB-in transfers are allocated, added to the parent->rx_submitted anchor and submitted. In the complete callback gs_usb_receive_bulk_callback(), the URB is processed and resubmitted. In gs_can_close() the URBs are freed by calling usb_kill_anchored_urbs(parent->rx_submitted). However, this does not take into account that the USB framework unanchors the URB before the complete function is called. This means that once an in-URB has been completed, it is no longer anchored and is ultimately not released in gs_can_close(). Fix the memory leak by anchoring the URB in the gs_usb_receive_bulk_callback() to the parent->rx_submitted anchor. Fixes: d08e973a77d1 ("can: gs_usb: Added support for the GS_USB CAN devices") Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260105-gs_usb-fix-memory-leak-v2-1-cc6ed6438034@pengutronix.de Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-09pinctrl: meson: extend build coverage with COMPILE_TEST=yBartosz Golaszewski
We currently only build these drivers on ARM but there's nothing that should stop us from building it with allmodconfig on other architectures. Extend the build coverage for all meson drivers. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-09can: etas_es58x: allow partial RX URB allocation to succeedSzymon Wilczek
When es58x_alloc_rx_urbs() fails to allocate the requested number of URBs but succeeds in allocating some, it returns an error code. This causes es58x_open() to return early, skipping the cleanup label 'free_urbs', which leads to the anchored URBs being leaked. As pointed out by maintainer Vincent Mailhol, the driver is designed to handle partial URB allocation gracefully. Therefore, partial allocation should not be treated as a fatal error. Modify es58x_alloc_rx_urbs() to return 0 if at least one URB has been allocated, restoring the intended behavior and preventing the leak in es58x_open(). Fixes: 8537257874e9 ("can: etas_es58x: add core support for ETAS ES58X CAN USB interfaces") Reported-by: syzbot+e8cb6691a7cf68256cb8@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=e8cb6691a7cf68256cb8 Signed-off-by: Szymon Wilczek <swilczek.lx@gmail.com> Reviewed-by: Vincent Mailhol <mailhol@kernel.org> Link: https://patch.msgid.link/20251223011732.39361-1-swilczek.lx@gmail.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-09dt-bindings: pinctrl: intel: keembay: fix typoAkiyoshi Kurita
Fix a typo in the documentation ("upto" -> "up to"). Signed-off-by: Akiyoshi Kurita <weibu@redadmin.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-01-09gpio: line-mux: remove bits already handled by GPIO coreBartosz Golaszewski
GPIO core already handles checking the offset against the number of GPIOs as well as missing any of the GPIO chip callbacks. Remove the unnecessary bits. Also, the offset check was off-by-one as reported by Dan. Fixes: 2b03d9a40cd1 ("gpio: add gpio-line-mux driver") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/aV4b6GAGz1zyf8Xy@stanley.mountain/ Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com> Reviewed-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://lore.kernel.org/r/20260107085833.17338-1-bartosz.golaszewski@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-01-09gpio: shared: fix a false-positive sharing detection with reset-gpiosBartosz Golaszewski
After scanning the devicetree, we remove all entries that have only one reference, while creating GPIO shared proxies for the remaining, shared entries. However: for the reset-gpio corner-case, we will have two references for a "reset-gpios" pin that's not really shared. In this case one will come from the actual consumer fwnode and the other from the potential auxiliary reset-gpio device. This causes the GPIO core to create unnecessary GPIO shared proxy devices for pins that are not really shared. Add a function that can detect this situation and remove entries that have exactly two references but one of them is a reset-gpio. Fixes: 7b78b26757e0 ("gpio: shared: handle the reset-gpios corner case") Link: https://lore.kernel.org/r/20260108-gpio-shared-false-positive-v1-1-5dbf8d1b2f7d@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-01-09drm/panic: Fix expected string for QR_CODE in drm_panic_type_mapNathan Chancellor
The help text of CONFIG_DRM_PANIC_SCREEN_QR_CODE documents the expected value to CONFIG_DRM_PANIC_SCREEN as "qr_code" but drm_panic_type_map checks for "qr". Adjust drm_panic_type_map and the module description to match so that existing configurations do not stop working. Fixes: e85e9ccf3f84 ("drm/panic: Report invalid or unsupported panic modes") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20260105-drm_panic-handle-invalid-drm_panic_screen-v1-2-55228bd4b0f8@kernel.org
2026-01-09drm/panic: Ensure drm_panic_type is initialized to a valid valueNathan Chancellor
If a user has set an invalid CONFIG_DRM_PANIC_SCREEN value (such as "qr_code" without CONFIG_DRM_PANIC_SCREEN_QR_CODE=y due to missing or incorrect Rust dependencies), there is a panic when accessing /sys/module/drm/parameters/panic_screen: [ 12.218375] BUG: unable to handle page fault for address: 0000000796dd8818 [ 12.219737] #PF: supervisor read access in kernel mode ... [ 12.227167] RIP: 0010:drm_panic_type_get+0x1b/0x30 If drm_panic_type_set() does not find a valid drm_panic_type enumeration in drm_panic_type_map based on the provided value, it does not change drm_panic_type from the default -1 value, which is not a valid index for accessing drm_panic_type_map in drm_panic_type_get(), resulting in the crash. Validate the value of CONFIG_DRM_PANIC_SCREEN at boot time via the return value of drm_panic_type_set() in drm_panic_init() and explicitly fall back to the default of "user" with a message to the user so that they can adjust their configuration or fix missing dependencies. [ 0.800697] Unsupported value for CONFIG_DRM_PANIC_SCREEN ('qr_code'), falling back to 'user'... Fixes: e85e9ccf3f84 ("drm/panic: Report invalid or unsupported panic modes") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20260105-drm_panic-handle-invalid-drm_panic_screen-v1-1-55228bd4b0f8@kernel.org
2026-01-09ARM: dts: lpc32xx: Add missing properties to I2S device tree nodesPiotr Wojtaszczyk
Add NXP LPC32xx I2S controller device tree properties in accordance to nxp,lpc3220-i2s.yaml. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-7-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> [vzapolskiy: changes to the commit message] Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controllerVladimir Zapolskiy
Add 'lli-bus-interface-ahb2' and 'mem-bus-interface-ahb2' properties to the PL080 DMA controller device tree node, tested with dmatest utility. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Add missing DMA propertiesPiotr Wojtaszczyk
Add properties declared in the new DT binding nxp,lpc3220-dmamux.yaml and corresponding phandles. [vzapolskiy]: 1. rebased the change, 2. dmamux unit address shall be 0x78 instead of 0x7c, 3. removed unsupported 'dmas' properties from sd, ssp0, ssp1 and HS UARTs, 4. more non-functional updates by reordering properies, 5. minor updates to the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-6-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Use syscon for system control blockPiotr Wojtaszczyk
The clock controller is a part of NXP LPC32xx system control block (SCB), and SCB provides a number of controllers apart of the clock controller. [vzapolskiy]: 1. kept a simple comment, 2. renamed SoC specific compatible to 'nxp,lpc3220-scb' due to the SoC UM, 3. changed size in 'ranges', since it should cover more SCB functions, 4. updated the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-5-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controllerVladimir Zapolskiy
SLC and MLC NAND flash controllers fire the muxed interrupt FLASH_INT to the SoC, add the interrupt property to the SLC device tree node. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: change NAND controllers node namesVladimir Zapolskiy
The device tree node name of NAND controllers shall be 'nand-controller', while 'flash' name is the name of NAND chip device tree nodes. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: lpc32xx: Update spi clock propertiesKuldeep Singh
PL022 binding require two clocks to be defined but NXP LPC32xx platform doesn't comply with the bindings and define only one clock i.e apb_pclk. Update SPI clocks and clocks-names property by adding appropriate clock reference to make it compliant with the bindings. Noteworthy, strictly speaking the change tackles DT ABI by changing the order in the list of clock-names property values, however this level of impact is considered as acceptable. Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com> [vzapolskiy: rebased and minor update to the commit message] Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2026-01-09ARM: dts: Add support for pcb8385Horatiu Vultur
Add basic support for pcb8385 [1]. It is a modular board which allows to add different daughter cards on which there are different PHYs. This adds support for UART, LEDs and I2C. [1] https://www.microchip.com/en-us/development-tool/ev83e85a Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20251208083545.3642168-3-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-09dt-bindings: arm: at91: add lan966 pcb8385 boardHoratiu Vultur
Add documentation for Microchip LAN9668 PCB8385 Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20251208083545.3642168-2-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-09wifi: rtw89: fw: set RACK bit every 4 H2C command for WiFi 6 chips onlyPing-Ke Shih
RACK is to ask firmware send received ACK to driver when a H2C command is received. This is necessary for WiFi 6 chips only. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-11-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: consider hardware AID for firmware elementsPing-Ke Shih
The coming chip RTL8922D has variant of hardware with different AID. Add AID field to header of firmware elements, and compare AID with the value read from hardware. Currently, apply this rule to BB and RF parameters. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-10-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add CMAC H2C command for punctured for RTL8922DPing-Ke Shih
CMAC H2C command is to configure CMAC such as TX retry and padding. Add to update CMAC function block while puncturing is changing. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-9-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add CMAC H2C command for TX time for RTL8922DPing-Ke Shih
CMAC H2C command is to configure CMAC such as TX retry and padding. Add to update CMAC function block when BT-coex want shorter TX time due to timeslot assignment, or when MCC want higher retry time to improve connection rate. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-8-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add CMAC H2C command for TX AMPDU for RTL8922DPing-Ke Shih
CMAC H2C command is to configure CMAC such as TX retry and padding. Add to update CMAC function block while AMPDU is established. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-7-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add CMAC H2C command for association for RTL8922DPing-Ke Shih
CMAC H2C command is to configure CMAC such as TX retry and padding. Add to update CMAC function block according to associated peer. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-6-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add CMAC H2C command to initialize default value for RTL8922DPing-Ke Shih
CMAC H2C command is to configure CMAC such as TX retry and padding. Add to reset CMAC function block to default value. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-5-pkshih@realtek.com
2026-01-09wifi: rtw89: fw: add DMAC v3 H2C command for RTL8922DPing-Ke Shih
Write association data including address and security key of peer to hardware. Add the command for RTL8922D accordingly. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-4-pkshih@realtek.com
2026-01-09wifi: rtw89: update query RXDESC v3 for RTL8922DPing-Ke Shih
Add RXDESC v3 to parse meta data of receiving packets for RTL8922D. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-3-pkshih@realtek.com
2026-01-09wifi: rtw89: update TXWD v3 for RTL8922DPing-Ke Shih
Add TXWD v3 to assist in transmitting for RTL8922D according to hardware design. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260106030911.15528-2-pkshih@realtek.com
2026-01-09Merge tag 'drm-misc-next-2026-01-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.20: UAPI Changes: Cross-subsystem Changes: Core Changes: - draw: Add API to check if a format conversion can be done - panic: Rename draw_panic_static_* to draw_panic_screen_*, Add kunit tests - shmem: Improve tests Driver Changes: - ast: Big endian fixes - etnaviv: Add PPU flop reset support - panfrost: Add GPU_PM_RT support for RZ/G3E SoC - panthor: multiple fixes around VM termination, huge page support - pl111: Fix build regression - v3d: Fix DMA segment size - bridge: - Add connector argument to .hpd_notify - Plenty of patches to convert existing drivers to refcounting - Convert Rockchip's inno hdmi support to a proper bridge - lontium-lt9611uxc: Switch to HDMI audio helpers - panel: - New panel: BOE NV140WUM-T08 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://patch.msgid.link/20260108-literate-nyala-of-courtesy-de501a@houat
2026-01-09dmaengine: xilinx: xdma: use sg_nents_for_dma() helperAndy Shevchenko
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-14-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-09dmaengine: sh: use sg_nents_for_dma() helperAndy Shevchenko
Instead of open coded variant let's use recently introduced helper. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20260108105619.3513561-13-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.51.0) at 2026-11-09 02:32:17 +0000