kernel.git/tools/testing/selftests/riscv/vector/Makefile, branch linux-rolling-lts

selftests: riscv: Fix vector tests

2025-01-18T20:33:37Z

Overhaul the riscv vector tests to use kselftest_harness to help the test cases correctly report the results and decouple the individual test cases from each other. With this refactoring, only run the test cases if vector is reported and properly report the test case as skipped otherwise. The v_initval_nolibc test was previously not checking if vector was supported and used a function (malloc) which invalidates the state of the vector registers. Signed-off-by: Charlie Jenkins Tested-by: Yangyu Chen Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com Signed-off-by: Palmer Dabbelt

selftests: Test RISC-V Vector's first-use handler

2023-07-01T14:38:22Z

This add a test to check if the kernel zero-initializes all V registers after the first-use trap handler returns. If V registers are not zero-initialized, then the test should fail one out of several runs: ``` root@sifive-fpga:~# ./v_initval_nolibc # vl = 256 not ok 1 detect stale values on v-regesters 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4c 41 4e 47 3d 43 0 50 41 54 48 3d 2f 75 73 72 2f 6c 6f 63 61 6c 2f 73 62 69 6e 3a 2f 75 73 72 2f 6c 6f 63 61 6c 2f 62 69 6e 3a 2f 75 73 72 ff ff 81 0 0 0 0 0 0 0 0 0 0 0 0 0 ``` Otherwise, the test passes without errors each run. Signed-off-by: Andy Chiu Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20230627015556.12329-3-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt

selftests: Test RISC-V Vector prctl interface

2023-06-08T14:16:58Z

This add a test for prctl interface that controls the use of userspace Vector. Signed-off-by: Andy Chiu Link: https://lore.kernel.org/r/20230605110724.21391-27-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt