kernel.git/tools/testing/selftests/powerpc, branch linux-5.18.y

selftests/powerpc: Skip energy_scale_info test on older firmware

2022-08-17T12:42:00Z

[ Upstream commit 4228a996b072d36f3baafb4afdc2d2d66d2cbadf ] Older machines don't have the firmware feature that enables the code this test is testing. Skip the test if the sysfs directory doesn't exist. Also use the FAIL_IF() macro to provide more verbose error reporting if an error is encountered. Fixes: 57201d657eb7 ("selftest/powerpc: Add PAPR sysfs attributes sniff test") Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220619233103.2666171-1-mpe@ellerman.id.au Signed-off-by: Sasha Levin

selftest/powerpc: Add PAPR sysfs attributes sniff test

2022-03-07T13:05:00Z

Include a testcase to check if the sysfs files for energy and frequency related have its related attribute files exist and populated Signed-off-by: Pratik R. Sampat Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220217105321.52941-3-psampat@linux.ibm.com

selftests/powerpc: Add test for real address error handling

2022-03-07T13:04:59Z

Add test for real address or control memory address access error handling, using NX-GZIP engine. The error is injected by accessing the control memory address using illegal instruction, on successful handling the process attempting to access control memory address using illegal instruction receives SIGBUS. Signed-off-by: Ganesh Goudar Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220107141428.67862-2-ganeshgr@linux.ibm.com

selftests/powerpc/pmu: Add interface test for mmcra register fields

2022-03-01T12:40:58Z

The testcase uses event code 0x35340401e0 to verify the settings for different fields in Monitor Mode Control Register A (MMCRA). The fields include thresh_start, thresh_stop thresh_select, sdar mode, sample and marked bit. Checks if these fields are translated correctly via perf interface to MMCRA. Signed-off-by: Kajol Jain [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-21-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr3_src fields

2022-03-01T12:40:47Z

The testcase uses event code 0x1340000001c040 to verify the settings for different src fields in Monitor Mode Control Register 3 (MMCR3). Checks if these fields are translated correctly via perf interface to MMCR3 on ISA v3.1 platform. Signed-off-by: Kajol Jain [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-20-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr2_fcs_fch fields

2022-03-01T12:40:36Z

The testcases uses cycles event to verify the freeze counter settings in Monitor Mode Control Register 2 (MMCR2). Event modifier (exclude_kernel) setting is used for the event attribute to check the FCxS and FCxH ( Freeze counter in privileged and hypervisor state ) settings via perf interface. Signed-off-by: Madhavan Srinivasan [mpe: Add error checking, check MSR for MSR_HV, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-19-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr2_l2l3 field

2022-03-01T12:40:26Z

The testcases uses event code 0x010000046080 to verify the l2l3 bit setting for Monitor Mode Control Register 2 (MMCR2). check if this bit is set correctly via perf interface in ISA v3.1 platform. Signed-off-by: Madhavan Srinivasan [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-18-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr1_comb field

2022-03-01T12:40:16Z

The testcase uses event code "0x26880" to verify the settings for different fields in Monitor Mode Control Register 1 (MMCR1). The field include PMCxCOMB. Checks if this field are translated correctly via perf interface to MMCR1 Add selftest for mmcr1 comb field. Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-16-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr0_pmc56 using pmc5

2022-03-01T12:40:06Z

The testcase uses event code 0x500fa to verify the FC5-6 bit setting in Monitor Mode Control Register 0 (MMCR0). Check if FC5-6 bit is not set in MMCR0 when using Performance Monitor Counter 5 and 6 (PMC5 and PMC6). Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-15-kjain@linux.ibm.com

selftests/powerpc/pmu/: Add interface test for mmcr0_fc56 field using pmc1

2022-03-01T12:39:54Z

The testcase uses event code 0x1001e to verify two bit settings (FC5-6 and PMC1CE) in Monitor Mode Control Register 0 (MMCR0). Check if FC5-6 bit to be set in MMCR0 when not using Performance Monitor Counter 5 and 6 (PMC5 and PMC6). And also PMC1CE is expected to be set when using PMC1. Test if these fields are programmed correctly via perf interface. Signed-off-by: Athira Rajeev [mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220127072012.662451-14-kjain@linux.ibm.com