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<title>kernel.git/tools/testing/selftests/kvm/lib/riscv/processor.c, branch linux-5.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.17.y</id>
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<updated>2022-04-20T07:36:14Z</updated>
<entry>
<title>KVM: selftests: riscv: Fix alignment of the guest_hang() function</title>
<updated>2022-04-20T07:36:14Z</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2022-04-09T03:45:51Z</published>
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<id>urn:sha1:fb80e2399d64ea70ad50ee93d8ec31cdd068ea85</id>
<content type='text'>
[ Upstream commit ebdef0de2dbc40e697adaa6b3408130f7a7b8351 ]

The guest_hang() function is used as the default exception handler
for various KVM selftests applications by setting it's address in
the vstvec CSR. The vstvec CSR requires exception handler base address
to be at least 4-byte aligned so this patch fixes alignment of the
guest_hang() function.

Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: selftests: Add initial support for RISC-V 64-bit</title>
<updated>2022-01-06T09:47:50Z</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2021-10-05T12:39:56Z</published>
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<id>urn:sha1:3e06cdf10520e629e711b76b21070d6e67ae7d06</id>
<content type='text'>
We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test

All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-and-tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
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