<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/tools/arch/x86/include, branch linux-5.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.9.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.9.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2020-12-11T12:22:10Z</updated>
<entry>
<title>x86/uprobes: Do not use prefixes.nbytes when looping over prefixes.bytes</title>
<updated>2020-12-11T12:22:10Z</updated>
<author>
<name>Masami Hiramatsu</name>
</author>
<published>2020-12-03T04:50:37Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5655e4c9c96aaa469cdcc0747cbcc11bc78d339d'/>
<id>urn:sha1:5655e4c9c96aaa469cdcc0747cbcc11bc78d339d</id>
<content type='text'>
commit 4e9a5ae8df5b3365183150f6df49e49dece80d8c upstream.

Since insn.prefixes.nbytes can be bigger than the size of
insn.prefixes.bytes[] when a prefix is repeated, the proper check must
be

  insn.prefixes.bytes[i] != 0 and i &lt; 4

instead of using insn.prefixes.nbytes.

Introduce a for_each_insn_prefix() macro for this purpose. Debugged by
Kees Cook &lt;keescook@chromium.org&gt;.

 [ bp: Massage commit message, sync with the respective header in tools/
   and drop "we". ]

Fixes: 2b1444983508 ("uprobes, mm, x86: Add the ability to install and remove uprobes breakpoints")
Reported-by: syzbot+9b64b619f10f19d19a7c@syzkaller.appspotmail.com
Signed-off-by: Masami Hiramatsu &lt;mhiramat@kernel.org&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Srikar Dronamraju &lt;srikar@linux.vnet.ibm.com&gt;
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/160697103739.3146288.7437620795200799020.stgit@devnote2
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}()</title>
<updated>2020-11-04T17:09:05Z</updated>
<author>
<name>Dan Williams</name>
</author>
<published>2020-10-06T03:40:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5fec7e5a28627138223aa20f5ff484898955ff77'/>
<id>urn:sha1:5fec7e5a28627138223aa20f5ff484898955ff77</id>
<content type='text'>
commit ec6347bb43395cb92126788a1a5b25302543f815 upstream.

In reaction to a proposal to introduce a memcpy_mcsafe_fast()
implementation Linus points out that memcpy_mcsafe() is poorly named
relative to communicating the scope of the interface. Specifically what
addresses are valid to pass as source, destination, and what faults /
exceptions are handled.

Of particular concern is that even though x86 might be able to handle
the semantics of copy_mc_to_user() with its common copy_user_generic()
implementation other archs likely need / want an explicit path for this
case:

  On Fri, May 1, 2020 at 11:28 AM Linus Torvalds &lt;torvalds@linux-foundation.org&gt; wrote:
  &gt;
  &gt; On Thu, Apr 30, 2020 at 6:21 PM Dan Williams &lt;dan.j.williams@intel.com&gt; wrote:
  &gt; &gt;
  &gt; &gt; However now I see that copy_user_generic() works for the wrong reason.
  &gt; &gt; It works because the exception on the source address due to poison
  &gt; &gt; looks no different than a write fault on the user address to the
  &gt; &gt; caller, it's still just a short copy. So it makes copy_to_user() work
  &gt; &gt; for the wrong reason relative to the name.
  &gt;
  &gt; Right.
  &gt;
  &gt; And it won't work that way on other architectures. On x86, we have a
  &gt; generic function that can take faults on either side, and we use it
  &gt; for both cases (and for the "in_user" case too), but that's an
  &gt; artifact of the architecture oddity.
  &gt;
  &gt; In fact, it's probably wrong even on x86 - because it can hide bugs -
  &gt; but writing those things is painful enough that everybody prefers
  &gt; having just one function.

Replace a single top-level memcpy_mcsafe() with either
copy_mc_to_user(), or copy_mc_to_kernel().

Introduce an x86 copy_mc_fragile() name as the rename for the
low-level x86 implementation formerly named memcpy_mcsafe(). It is used
as the slow / careful backend that is supplanted by a fast
copy_mc_generic() in a follow-on patch.

One side-effect of this reorganization is that separating copy_mc_64.S
to its own file means that perf no longer needs to track dependencies
for its memcpy_64.S benchmarks.

 [ bp: Massage a bit. ]

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Acked-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Link: http://lore.kernel.org/r/CAHk-=wjSqtXAqfUJxFtWNwmguFASTgB0dz1dT3V-78Quiezqbg@mail.gmail.com
Link: https://lkml.kernel.org/r/160195561680.2163339.11574962055305783722.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Revert "x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}()"</title>
<updated>2020-11-04T17:08:28Z</updated>
<author>
<name>Greg Kroah-Hartman</name>
</author>
<published>2020-11-04T17:05:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8b5145ba3afc24f9749e57d3c0e6bba0b129dc4d'/>
<id>urn:sha1:8b5145ba3afc24f9749e57d3c0e6bba0b129dc4d</id>
<content type='text'>
This reverts commit a85748ed9eb70108f9605558f2754ca94ee91401 which is
commit ec6347bb43395cb92126788a1a5b25302543f815 upstream.

We had a mistake when merging a later patch in this series due to some
file movements, so revert this change for now, as we will add it back in
a later commit.

Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}()</title>
<updated>2020-11-01T11:47:03Z</updated>
<author>
<name>Dan Williams</name>
</author>
<published>2020-10-06T03:40:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a85748ed9eb70108f9605558f2754ca94ee91401'/>
<id>urn:sha1:a85748ed9eb70108f9605558f2754ca94ee91401</id>
<content type='text'>
commit ec6347bb43395cb92126788a1a5b25302543f815 upstream.

In reaction to a proposal to introduce a memcpy_mcsafe_fast()
implementation Linus points out that memcpy_mcsafe() is poorly named
relative to communicating the scope of the interface. Specifically what
addresses are valid to pass as source, destination, and what faults /
exceptions are handled.

Of particular concern is that even though x86 might be able to handle
the semantics of copy_mc_to_user() with its common copy_user_generic()
implementation other archs likely need / want an explicit path for this
case:

  On Fri, May 1, 2020 at 11:28 AM Linus Torvalds &lt;torvalds@linux-foundation.org&gt; wrote:
  &gt;
  &gt; On Thu, Apr 30, 2020 at 6:21 PM Dan Williams &lt;dan.j.williams@intel.com&gt; wrote:
  &gt; &gt;
  &gt; &gt; However now I see that copy_user_generic() works for the wrong reason.
  &gt; &gt; It works because the exception on the source address due to poison
  &gt; &gt; looks no different than a write fault on the user address to the
  &gt; &gt; caller, it's still just a short copy. So it makes copy_to_user() work
  &gt; &gt; for the wrong reason relative to the name.
  &gt;
  &gt; Right.
  &gt;
  &gt; And it won't work that way on other architectures. On x86, we have a
  &gt; generic function that can take faults on either side, and we use it
  &gt; for both cases (and for the "in_user" case too), but that's an
  &gt; artifact of the architecture oddity.
  &gt;
  &gt; In fact, it's probably wrong even on x86 - because it can hide bugs -
  &gt; but writing those things is painful enough that everybody prefers
  &gt; having just one function.

Replace a single top-level memcpy_mcsafe() with either
copy_mc_to_user(), or copy_mc_to_kernel().

Introduce an x86 copy_mc_fragile() name as the rename for the
low-level x86 implementation formerly named memcpy_mcsafe(). It is used
as the slow / careful backend that is supplanted by a fast
copy_mc_generic() in a follow-on patch.

One side-effect of this reorganization is that separating copy_mc_64.S
to its own file means that perf no longer needs to track dependencies
for its memcpy_64.S benchmarks.

 [ bp: Massage a bit. ]

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Acked-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Link: http://lore.kernel.org/r/CAHk-=wjSqtXAqfUJxFtWNwmguFASTgB0dz1dT3V-78Quiezqbg@mail.gmail.com
Link: https://lkml.kernel.org/r/160195561680.2163339.11574962055305783722.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>tools arch x86: Sync asm/cpufeatures.h with the kernel sources</title>
<updated>2020-08-07T11:56:59Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-08-07T11:56:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dd4a5c224b7c9bdf06e5423d5cd19a9f8b9a3558'/>
<id>urn:sha1:dd4a5c224b7c9bdf06e5423d5cd19a9f8b9a3558</id>
<content type='text'>
To pick up the changes from:

  85b23fbc7d88 ("x86/cpufeatures: Add enumeration for SERIALIZE instruction")
  bd657aa3dd85 ("x86/cpufeatures: Add Architectural LBRs feature bit")
  fbd5969d1ff2 ("x86/cpufeatures: Mark two free bits in word 3")

These should't cause any changes in tooling, it just gets rebuilt by
including those headers:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o
  LD       /tmp/build/perf/bench/perf-in.o
  LD       /tmp/build/perf/perf-in.o
  LINK     /tmp/build/perf/perf

And silences this perf build warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Ricardo Neri &lt;ricardo.neri-calderon@linux.intel.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools arch x86: Sync the msr-index.h copy with the kernel sources</title>
<updated>2020-08-07T11:45:47Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-08-07T11:45:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f815fe512cf71fa611016f467fde808a6ee67e35'/>
<id>urn:sha1:f815fe512cf71fa611016f467fde808a6ee67e35</id>
<content type='text'>
To pick up the changes in:

  d6a162a41bfd x86/msr-index: Add bunch of MSRs for Arch LBR
  ed7bde7a6dab cpufreq: intel_pstate: Allow enable/disable energy efficiency
  99e40204e014 (tip/x86/cleanups) x86/msr: Move the F15h MSRs where they belong
  1068ed4547ad x86/msr: Lift AMD family 0x15 power-specific MSRs
  5cde265384ca (tag: perf-core-2020-06-01) perf/x86/rapl: Add AMD Fam17h RAPL support

Addressing these tools/perf build warnings:

That makes the beautification scripts to pick some new entries:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh &gt; before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh &gt; after
  $ diff -u before after
  --- before	2020-08-07 08:45:18.801298854 -0300
  +++ after	2020-08-07 08:45:28.654456422 -0300
  @@ -271,6 +271,8 @@
   	[0xc0010062 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_CTL",
   	[0xc0010063 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_STATUS",
   	[0xc0010064 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PSTATE_DEF_BASE",
  +	[0xc001007a - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_PWR_ACCUMULATOR",
  +	[0xc001007b - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_MAX_PWR_ACCUMULATOR",
   	[0xc0010112 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_ADDR",
   	[0xc0010113 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_MASK",
   	[0xc0010114 - x86_AMD_V_KVM_MSRs_offset] = "VM_CR",
  $

And this gets rebuilt:

  CC       /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o
  INSTALL  trace_plugins
  LD       /tmp/build/perf/trace/beauty/tracepoints/perf-in.o
  LD       /tmp/build/perf/trace/beauty/perf-in.o
  LD       /tmp/build/perf/perf-in.o
  LINK     /tmp/build/perf/perf

Now one can trace systemwide asking to see backtraces to where those
MSRs are being read/written with:

  # perf trace -e msr:*_msr/max-stack=32/ --filter="msr==F15H_CU_PWR_ACCUMULATOR || msr==F15H_CU_MAX_PWR_ACCUMULATOR"
  ^C#
  #

If we use -v (verbose mode) we can see what it does behind the scenes:

  # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==F15H_CU_PWR_ACCUMULATOR || msr==F15H_CU_MAX_PWR_ACCUMULATOR"
  Using CPUID GenuineIntel-6-8E-A
  0xc001007a
  0xc001007b
  New filter for msr:read_msr: (msr==0xc001007a || msr==0xc001007b) &amp;&amp; (common_pid != 2448054 &amp;&amp; common_pid != 2782)
  0xc001007a
  0xc001007b
  New filter for msr:write_msr: (msr==0xc001007a || msr==0xc001007b) &amp;&amp; (common_pid != 2448054 &amp;&amp; common_pid != 2782)
  mmap size 528384B
  ^C#

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Cc: Srinivas Pandruvada &lt;srinivas.pandruvada@linux.intel.com&gt;
Cc: Stephane Eranian &lt;eranian@google.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools arch kvm: Sync kvm headers with the kernel sources</title>
<updated>2020-07-17T12:39:16Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-07-17T12:39:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=25d4e7f513d4f8afcf81cb6f00edf1248b0ff8fc'/>
<id>urn:sha1:25d4e7f513d4f8afcf81cb6f00edf1248b0ff8fc</id>
<content type='text'>
To pick up the changes from:

  83d31e5271ac ("KVM: nVMX: fixes for preemption timer migration")

That don't entail changes in tooling.

This silences these tools/perf build warnings:

  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/kvm.h' differs from latest version at 'arch/x86/include/uapi/asm/kvm.h'
  diff -u tools/arch/x86/include/uapi/asm/kvm.h arch/x86/include/uapi/asm/kvm.h

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools arch x86: Sync the msr-index.h copy with the kernel sources</title>
<updated>2020-06-17T16:21:26Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-06-17T13:07:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=25ca7e5c0b0315f3b5e6c4d2123e5a821ec0b590'/>
<id>urn:sha1:25ca7e5c0b0315f3b5e6c4d2123e5a821ec0b590</id>
<content type='text'>
To pick up the changes in:

  7e5b3c267d25 ("x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation")

Addressing these tools/perf build warnings:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h

With this one will be able to use these new AMD MSRs in filters, by
name, e.g.:

  # perf trace -e msr:* --filter "msr==IA32_MCU_OPT_CTRL"
  ^C#

Using -v we can see how it sets up the tracepoint filters, converting
from the string in the filter to the numeric value:

  # perf trace -v -e msr:* --filter "msr==IA32_MCU_OPT_CTRL"
  Using CPUID GenuineIntel-6-8E-A
  0x123
  New filter for msr:read_msr: (msr==0x123) &amp;&amp; (common_pid != 335 &amp;&amp; common_pid != 30344)
  0x123
  New filter for msr:write_msr: (msr==0x123) &amp;&amp; (common_pid != 335 &amp;&amp; common_pid != 30344)
  0x123
  New filter for msr:rdpmc: (msr==0x123) &amp;&amp; (common_pid != 335 &amp;&amp; common_pid != 30344)
  mmap size 528384B
  ^C#

The updating process shows how this affects tooling in more detail:

  $ diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
  --- tools/arch/x86/include/asm/msr-index.h	2020-06-03 10:36:09.959910238 -0300
  +++ arch/x86/include/asm/msr-index.h	2020-06-17 10:04:20.235052901 -0300
  @@ -128,6 +128,10 @@
   #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
   #define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */

  +/* SRBDS support */
  +#define MSR_IA32_MCU_OPT_CTRL		0x00000123
  +#define RNGDS_MITG_DIS			BIT(0)
  +
   #define MSR_IA32_SYSENTER_CS		0x00000174
   #define MSR_IA32_SYSENTER_ESP		0x00000175
   #define MSR_IA32_SYSENTER_EIP		0x00000176
  $ set -o vi
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh &gt; before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh &gt; after
  $ diff -u before after
  --- before	2020-06-17 10:05:49.653114752 -0300
  +++ after	2020-06-17 10:06:01.777258731 -0300
  @@ -51,6 +51,7 @@
   	[0x0000011e] = "IA32_BBL_CR_CTL3",
   	[0x00000120] = "IDT_MCR_CTRL",
   	[0x00000122] = "IA32_TSX_CTRL",
  +	[0x00000123] = "IA32_MCU_OPT_CTRL",
   	[0x00000140] = "MISC_FEATURES_ENABLES",
   	[0x00000174] = "IA32_SYSENTER_CS",
   	[0x00000175] = "IA32_SYSENTER_ESP",
  $

The related change to cpu-features.h affects this:

  CC       /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
  CC       /tmp/build/perf/bench/mem-memset-x86-64-asm.o

This shouldn't be affecting that 'perf bench' entry:

  $ find tools/perf/ -type f | xargs grep SRBDS
  $

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Mark Gross &lt;mgross@linux.intel.com&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools headers UAPI: Sync kvm.h headers with the kernel sources</title>
<updated>2020-06-09T15:40:04Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-06-08T15:28:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=dd76c302955de405ea589e36c574f6f10eca99b6'/>
<id>urn:sha1:dd76c302955de405ea589e36c574f6f10eca99b6</id>
<content type='text'>
To pick the changes in:

  f97f5a56f597 ("x86/kvm/hyper-v: Add support for synthetic debugger interface")
  850448f35aaf ("KVM: nVMX: Fix VMX preemption timer migration")
  2c4c41325540 ("KVM: x86: Print symbolic names of VMX VM-Exit flags in traces")
  cc440cdad5b7 ("KVM: nSVM: implement KVM_GET_NESTED_STATE and KVM_SET_NESTED_STATE")
  f7d31e65368a ("x86/kvm/hyper-v: Explicitly align hcall param for kvm_hyperv_exit")
  72de5fa4c161 ("KVM: x86: announce KVM_FEATURE_ASYNC_PF_INT")
  acd05785e48c ("kvm: add capability for halt polling")
  3ecad8c2c1ff ("docs: fix broken references for ReST files that moved around")

That do not result in any change in tooling, as the additions are not
being used in any table generator.

This silences these perf build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/kvm.h' differs from latest version at 'include/uapi/linux/kvm.h'
  diff -u tools/include/uapi/linux/kvm.h include/uapi/linux/kvm.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/kvm.h' differs from latest version at 'arch/x86/include/uapi/asm/kvm.h'
  diff -u tools/arch/x86/include/uapi/asm/kvm.h arch/x86/include/uapi/asm/kvm.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/vmx.h' differs from latest version at 'arch/x86/include/uapi/asm/vmx.h'
  diff -u tools/arch/x86/include/uapi/asm/vmx.h arch/x86/include/uapi/asm/vmx.h

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: David Matlack &lt;dmatlack@google.com&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Jon Doron &lt;arilou@gmail.com&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Peter Shier &lt;pshier@google.com&gt;
Cc: Sean Christopherson &lt;sean.j.christopherson@intel.com&gt;
Cc: Vitaly Kuznetsov &lt;vkuznets@redhat.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools arch x86 uapi: Synch asm/unistd.h with the kernel sources</title>
<updated>2020-06-09T15:40:03Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
</author>
<published>2020-06-08T14:23:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7e579f3a074c9348389ea0cf0491264e1ffbc585'/>
<id>urn:sha1:7e579f3a074c9348389ea0cf0491264e1ffbc585</id>
<content type='text'>
To pick up the change in:

  700d3a5a664d ("x86/syscalls: Revert "x86/syscalls: Make __X32_SYSCALL_BIT be unsigned long"")

That doesn't trigger any changes in tooling and silences this perf build
warning:

  Warning: Kernel ABI header at 'tools/arch/x86/include/uapi/asm/unistd.h' differs from latest version at 'arch/x86/include/uapi/asm/unistd.h'
  diff -u tools/arch/x86/include/uapi/asm/unistd.h arch/x86/include/uapi/asm/unistd.h

Cc: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Cc: Andy Lutomirski &lt;luto@kernel.org&gt;
Cc: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Jiri Olsa &lt;jolsa@kernel.org&gt;
Cc: Namhyung Kim &lt;namhyung@kernel.org&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
</feed>
