<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/include/asm-mips/barrier.h, branch linux-2.6.23.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-2.6.23.y</id>
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<updated>2007-07-20T17:57:39Z</updated>
<entry>
<title>[MIPS] Make support for weakly ordered LL/SC a config option.</title>
<updated>2007-07-20T17:57:39Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2007-07-14T12:24:05Z</published>
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<id>urn:sha1:17099b1142f6c0359fca60a3464dea8fb30badea</id>
<content type='text'>
None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>[MIPS] Cleanup memory barriers for weakly ordered systems.</title>
<updated>2006-12-04T22:43:14Z</updated>
<author>
<name>Ralf Baechle</name>
</author>
<published>2006-10-31T03:45:07Z</published>
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<id>urn:sha1:0004a9dfeaa709a7f853487aba19932c9b1a87c8</id>
<content type='text'>
Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync
needed.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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