kernel.git/drivers/usb/dwc2/core.c, branch linux-3.16.y

usb: dwc2: Add function to calculate correct FIFO sizes

2014-05-27T22:42:42Z

The dwc2 IP on the SOCFPGA cannot use the default HW configured FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064 32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults to 0x2000 or 8192 32-bit words. So the driver cannot just use the fifo sizes as read from those registers. For platforms that face the same issue, this commits sets the RX, periodic TX, and non-periodic TX fifo size to those that are recommended v2.93a spec for the DWC2 IP. Implements Method #2 from the Synopsys v2.93a spec for the DWC2. Signed-off-by: Dinh Nguyen Acked-by: Paul Zimmerman Reviewed-by: Felipe Balbi Signed-off-by: Greg Kroah-Hartman

usb: dwc2: fix role switch breakage

2014-02-04T20:59:14Z

Commit beb7e592bc "staging: dwc2: add check on dwc2_core_reset return" broke the B -> A role switching on OTG-enabled platforms. This commit fixes it. Reported-by: Dinh Nguyen Tested-by: Dinh Nguyen Signed-off-by: Paul Zimmerman Signed-off-by: Greg Kroah-Hartman

Move DWC2 driver out of staging

2014-01-13T22:44:01Z

The DWC2 driver should now be in good enough shape to move out of staging. I have stress tested it overnight on RPI running mass storage and Ethernet transfers in parallel, and for several days on our proprietary PCI-based platform. Signed-off-by: Paul Zimmerman Cc: Felipe Balbi Signed-off-by: Greg Kroah-Hartman