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<title>kernel.git/drivers/soc/xilinx/Makefile, branch linux-5.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.16.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2021-02-09T02:31:25Z</updated>
<entry>
<title>clk: xilinx: move xlnx_vcu clock driver from soc</title>
<updated>2021-02-09T02:31:25Z</updated>
<author>
<name>Michael Tretter</name>
</author>
<published>2021-01-21T07:16:59Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a2fe7baa27a46533005bdf3580ca04f0276c175f'/>
<id>urn:sha1:a2fe7baa27a46533005bdf3580ca04f0276c175f</id>
<content type='text'>
The xlnx_vcu driver is actually a clock controller driver which provides
clocks that can be used by a driver for the encoder/decoder units. There
is no reason to keep this driver in soc. Move the driver to clk.

NOTE: The register mapping actually contains registers for AXI
performance monitoring, but these are not used by the driver.

Signed-off-by: Michael Tretter &lt;m.tretter@pengutronix.de&gt;
Acked-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>drivers: soc: xilinx: Add ZynqMP power domain driver</title>
<updated>2019-02-12T12:38:16Z</updated>
<author>
<name>Jolly Shah</name>
</author>
<published>2019-02-01T22:08:50Z</published>
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<id>urn:sha1:e23d9c6d0d4912fab12cd2d56070b0a8199772f0</id>
<content type='text'>
The zynqmp-genpd driver communicates the usage requirements
for logical power domains / devices to the platform FW.
FW is responsible for choosing appropriate power states,
taking Linux' usage information into account.

Signed-off-by: Rajan Vaja &lt;rajan.vaja@xilinx.com&gt;
Signed-off-by: Jolly Shah &lt;jolly.shah@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>drivers: soc: xilinx: Add ZynqMP PM driver</title>
<updated>2019-02-12T12:36:24Z</updated>
<author>
<name>Rajan Vaja</name>
</author>
<published>2019-01-29T20:38:21Z</published>
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<id>urn:sha1:ab272643d723f531b9caa8a4ac5f85fcd26840d2</id>
<content type='text'>
Add ZynqMP PM driver. PM driver provides power management
support for ZynqMP.

Signed-off-by: Rajan Vaja &lt;rajan.vaja@xilinx.com&gt;
Signed-off-by: Jolly Shah &lt;jolly.shah@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver</title>
<updated>2018-01-08T12:42:47Z</updated>
<author>
<name>Dhaval Shah</name>
</author>
<published>2017-12-21T18:33:06Z</published>
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<id>urn:sha1:cee8113a295acfc4cd25728d7c3d44e6bc3bbff9</id>
<content type='text'>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.

Signed-off-by: Dhaval Shah &lt;dshah@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>soc: xilinx: Create folder structure for soc specific drivers</title>
<updated>2018-01-08T12:42:39Z</updated>
<author>
<name>Michal Simek</name>
</author>
<published>2017-12-19T13:15:25Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5abcdc206fe8383f1e74d6cbce2f16ff0b121715'/>
<id>urn:sha1:5abcdc206fe8383f1e74d6cbce2f16ff0b121715</id>
<content type='text'>
Create directory structure with Makefile/Kconfig for adding xilinx soc
specific drivers.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
</feed>
