<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/soc/tegra/pmc.c, branch linux-5.8.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.8.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2020-05-22T12:55:54Z</updated>
<entry>
<title>soc/tegra: pmc: Enable PMIC wake event on Tegra210</title>
<updated>2020-05-22T12:55:54Z</updated>
<author>
<name>Jon Hunter</name>
</author>
<published>2020-05-20T15:13:17Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=df701a76a6419e66b566457a5b3fcdd314e48fd9'/>
<id>urn:sha1:df701a76a6419e66b566457a5b3fcdd314e48fd9</id>
<content type='text'>
The PMIC wake event can be used to bring the system out of suspend based
on certain events happening on the PMIC (such as an RTC alarm).

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Enable PMIC wake event on Tegra194</title>
<updated>2020-05-07T19:23:39Z</updated>
<author>
<name>Jon Hunter</name>
</author>
<published>2020-05-07T10:13:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=09701895aa93df32cc708eab032ae8704feda333'/>
<id>urn:sha1:09701895aa93df32cc708eab032ae8704feda333</id>
<content type='text'>
The PMIC wake event can be used to bring the system out of suspend based
on certain events happening on the PMIC (such as an RTC alarm).

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Enable PMIC wake event on Tegra186</title>
<updated>2020-04-21T22:04:19Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2020-04-17T17:11:16Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c78cf9956f19a7db7199310802ec514266653931'/>
<id>urn:sha1:c78cf9956f19a7db7199310802ec514266653931</id>
<content type='text'>
The PMIC wake event can be used to bring the system out of suspend based
on certain events happening on the PMIC (such as an RTC alarm).

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Cleanup whitespace usage</title>
<updated>2020-03-13T09:53:10Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2020-03-11T11:05:07Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4825f5354ef2e3f6bce61d0ed652a23daf379f8e'/>
<id>urn:sha1:4825f5354ef2e3f6bce61d0ed652a23daf379f8e</id>
<content type='text'>
Avoid using a mixture of tabs and spaces within tables to make them
easier to read and more consistently formatted.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Add pins for Tegra194</title>
<updated>2020-03-13T09:53:10Z</updated>
<author>
<name>Venkat Reddy Talla</name>
</author>
<published>2020-03-10T10:43:56Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=04fac2412ba413fc9f7f792baa0b67d92ff4d1a4'/>
<id>urn:sha1:04fac2412ba413fc9f7f792baa0b67d92ff4d1a4</id>
<content type='text'>
Extend the Tegra194 IO pad table with additional information such as pin
names and 1.8/3.3 V settings to allow a table of voltage control pins to
generated from it. This is similar to what's done for older chips and is
needed to support high-speed modes for SDHCI where switching the pins to
1.8V or 3.3V is necessary.

Signed-off-by: Venkat Reddy Talla &lt;vreddytalla@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add support for 32 kHz blink clock</title>
<updated>2020-03-13T09:53:06Z</updated>
<author>
<name>Sowjanya Komatineni</name>
</author>
<published>2020-01-14T07:24:15Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=03e917b2a025d6a676af4c2ae9c410c049bda161'/>
<id>urn:sha1:03e917b2a025d6a676af4c2ae9c410c049bda161</id>
<content type='text'>
Tegra PMC has blink control to output 32 kHz clock out to Tegra blink
pin. Blink pad DPD state and enable controls are part of Tegra PMC
register space.

Currently Tegra clock driver registers blink control by passing PMC
address and register offset to clk_register_gate which performs direct
PMC access during clk_ops and with this when PMC is in secure mode, any
access from non-secure world does not go through.

This patch adds blink control registration to the Tegra PMC driver using
PMC specific clock gate operations that use tegra_pmc_readl() and
tegra_pmc_writel() to support both secure mode and non-secure
mode PMC register access.

Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add Tegra PMC clocks registration into PMC driver</title>
<updated>2020-03-13T09:52:53Z</updated>
<author>
<name>Sowjanya Komatineni</name>
</author>
<published>2020-01-14T07:24:13Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=bd9638ed8e125482945a13a6d97522560edbc9b9'/>
<id>urn:sha1:bd9638ed8e125482945a13a6d97522560edbc9b9</id>
<content type='text'>
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.

With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.

This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.

clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.

Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>remove ioremap_nocache and devm_ioremap_nocache</title>
<updated>2020-01-06T08:45:59Z</updated>
<author>
<name>Christoph Hellwig</name>
</author>
<published>2020-01-06T08:43:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=4bdc0d676a643140bdf17dbf7eafedee3d496a3c'/>
<id>urn:sha1:4bdc0d676a643140bdf17dbf7eafedee3d496a3c</id>
<content type='text'>
ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Add reset sources and levels on Tegra194</title>
<updated>2019-11-18T12:56:58Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-11-18T06:33:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=48914c4ecb0c0fa1d70ea7b97d758ce5fadacfb0'/>
<id>urn:sha1:48914c4ecb0c0fa1d70ea7b97d758ce5fadacfb0</id>
<content type='text'>
Tegra194 supports the same reset levels as Tegra186 but extends the set
of reset sources. Provide custom PMC register definitions to account for
the larger field for the reset sources as well as the updated list of
reset sources.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
---
Changes in v2:
- use the new Tegra194 register definitions
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Add missing IRQ callbacks on Tegra194</title>
<updated>2019-11-18T12:55:56Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2019-11-18T06:33:47Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=cd4a709a19d58b7805b261ceac7bef94f423e08f'/>
<id>urn:sha1:cd4a709a19d58b7805b261ceac7bef94f423e08f</id>
<content type='text'>
Reuse the IRQ callbacks from Tegra186 on Tegra194. This fixes failures
to request interrupts on Tegra194 due to the missing callbacks.

Cc: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Fixes: aba19827fced ("soc/tegra: pmc: Support wake events on more Tegra SoCs")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
