kernel.git/drivers/soc/tegra/pmc.c, branch linux-5.6.y

remove ioremap_nocache and devm_ioremap_nocache

2020-01-06T08:45:59Z

ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig Acked-by: Arnd Bergmann

soc/tegra: pmc: Add reset sources and levels on Tegra194

2019-11-18T12:56:58Z

Tegra194 supports the same reset levels as Tegra186 but extends the set of reset sources. Provide custom PMC register definitions to account for the larger field for the reset sources as well as the updated list of reset sources. Signed-off-by: Thierry Reding --- Changes in v2: - use the new Tegra194 register definitions

soc/tegra: pmc: Add missing IRQ callbacks on Tegra194

2019-11-18T12:55:56Z

Reuse the IRQ callbacks from Tegra186 on Tegra194. This fixes failures to request interrupts on Tegra194 due to the missing callbacks. Cc: Sowjanya Komatineni Fixes: aba19827fced ("soc/tegra: pmc: Support wake events on more Tegra SoCs") Signed-off-by: Thierry Reding Acked-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Thierry Reding

soc/tegra: pmc: Use lower-case for hexadecimal literals

2019-11-18T12:55:21Z

The remainder of the file uses lower-case for hexadecimal literals, so change the only odd-one-out occurrence for consistency. Signed-off-by: Thierry Reding Acked-by: Jon Hunter Signed-off-by: Thierry Reding

soc/tegra: pmc: Remove unnecessary memory barrier

2019-10-29T13:36:24Z

The removed barrier isn't needed because writes/reads are strictly ordered and even if PMC had separate ports for writes, it wouldn't matter since the hardware logic takes into effect after triggering CPU's power-gating and at that point all CPU accesses are guaranteed to be completed. That barrier was copied from the old arch/ code during transition to the soc/ PMC driver and even that the code structure was different back then, the barrier didn't have a real useful purpose from the start. Lastly, the tegra_pmc_writel() naturally inserts wmb() because it uses writel(), and thus this change doesn't actually make any difference in terms of interacting with hardware. Hence let's remove the barrier to clean up code a tad. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

soc/tegra: pmc: Query PCLK clock rate at probe time

2019-10-29T13:35:06Z

It is possible to get a lockup if kernel decides to enter LP2 cpuidle from some clk-notifier, in that case CCF's "prepare" mutex is kept locked and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being disabled, hanging machine. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Thierry Reding

soc/tegra: pmc: Configure deep sleep control settings

2019-10-29T12:30:16Z

Tegra210 and prior Tegra chips have deep sleep entry and wakeup related timings which are platform specific that should be configured before entering into deep sleep. Below are the timing specific configurations for deep sleep entry and wakeup. - Core rail power-on stabilization timer - OSC clock stabilization timer after SOC rail power is stabilized. - Core power off time is the minimum wake delay to keep the system in deep sleep state irrespective of any quick wake event. These values depends on the discharge time of regulators and turn OFF time of the PMIC to allow the complete system to finish entering into deep sleep state. These values vary based on the platform design and are specified through the device tree. This patch has implementation to configure these timings which are must to have for proper deep sleep and wakeup operations. Signed-off-by: Sowjanya Komatineni Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding

soc/tegra: pmc: Configure core power request polarity

2019-10-29T12:29:59Z

This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding

soc/tegra: pmc: Add wake event support on Tegra210

2019-10-29T12:29:30Z

This patch implements PMC wakeup sequence for Tegra210 and defines the commonly used RTC alarm wake event. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding

soc/tegra: pmc: Support wake events on more Tegra SoCs

2019-10-29T12:26:35Z

This patch allows to create separate irq_set_wake and irq_set_type implementations for different Tegra designs PMC that has different wake models which require difference wake registers and different programming sequence. AOWAKE model support is available for Tegra186 and Tegra194 only and it resides within PMC and supports tiered wake architecture. Tegra210 and prior Tegra designs uses PMC directly to receive wake events and coordinate the wake sequence. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding