<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/soc/tegra/Kconfig, branch linux-5.10.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.10.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-5.10.y'/>
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<updated>2022-10-26T11:25:29Z</updated>
<entry>
<title>soc/tegra: fuse: Drop Kconfig dependency on TEGRA20_APB_DMA</title>
<updated>2022-10-26T11:25:29Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2020-09-23T00:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5bbd3dd7f92349cd836e64186dce7539348d88ac'/>
<id>urn:sha1:5bbd3dd7f92349cd836e64186dce7539348d88ac</id>
<content type='text'>
[ Upstream commit 2254182807fc09ba9dec9a42ef239e373796f1b2 ]

The DMA subsystem could be entirely disabled in Kconfig and then the
TEGRA20_APB_DMA option isn't available too. Hence kernel configuration
fails if DMADEVICES Kconfig option is disabled due to the unsatisfiable
dependency.

The FUSE driver isn't a critical driver and currently it only provides
NVMEM interface to userspace which isn't known to be widely used, and
thus, it's fine if FUSE driver fails to load.

Let's remove the erroneous Kconfig dependency and let the FUSE driver to
fail the probing if DMA is unavailable.

Fixes: 19d41e5e9c68 ("soc/tegra: fuse: Add APB DMA dependency for Tegra20")
Reported-by: Necip Fazil Yildiran &lt;fazilyildiran@gmail.com&gt;
Link: https://bugzilla.kernel.org/show_bug.cgi?id=209301
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Initial Tegra234 VDK support</title>
<updated>2020-09-18T13:58:07Z</updated>
<author>
<name>Thierry Reding</name>
</author>
<published>2020-09-17T10:07:52Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=639448912ba17a9af9e759efbab37d36c6e29dea'/>
<id>urn:sha1:639448912ba17a9af9e759efbab37d36c6e29dea</id>
<content type='text'>
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.

Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Select GENERIC_PINCONF</title>
<updated>2020-05-07T19:23:00Z</updated>
<author>
<name>Corentin Labbe</name>
</author>
<published>2020-03-18T15:25:08Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=5098e2b95e8e6f56266c2d5c180c75917090082a'/>
<id>urn:sha1:5098e2b95e8e6f56266c2d5c180c75917090082a</id>
<content type='text'>
I have hit the following build error:
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o: in function `pinconf_generic_dt_node_to_map_pin':
pmc.c:(.text+0x500): undefined reference to `pinconf_generic_dt_node_to_map'
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o:(.rodata+0x1f88): undefined reference to `pinconf_generic_dt_free_map'

So SOC_TEGRA_PMC should select GENERIC_PINCONF.

Fixes: 4a37f11c8f57 ("soc/tegra: pmc: Implement pad configuration via pinctrl")
Cc: stable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Corentin Labbe &lt;clabbe@baylibre.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add APB DMA dependency for Tegra20</title>
<updated>2020-01-10T14:30:11Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2019-12-29T15:01:21Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=19d41e5e9c6863ada69e4f6d006634e60987c7ac'/>
<id>urn:sha1:19d41e5e9c6863ada69e4f6d006634e60987c7ac</id>
<content type='text'>
Tegra20 FUSE driver depends on DMA channel presence, otherwise it fails to
probe.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: regulators: Add regulators coupler for Tegra30</title>
<updated>2019-10-29T13:02:59Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2019-07-25T15:18:32Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=783807436f363e5b1ad4d43ba7debbedfcadbb99'/>
<id>urn:sha1:783807436f363e5b1ad4d43ba7debbedfcadbb99</id>
<content type='text'>
Add regulators coupler for Tegra30 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
coupled regulator voltages shall be in a range of 300mV from each other
and CORE voltage shall be higher than the CPU by N mV, where N depends
on the CPU voltage.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: regulators: Add regulators coupler for Tegra20</title>
<updated>2019-10-29T13:02:59Z</updated>
<author>
<name>Dmitry Osipenko</name>
</author>
<published>2019-07-25T15:18:31Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=496747e7d907b01bd2507d61bdd6874b987c9629'/>
<id>urn:sha1:496747e7d907b01bd2507d61bdd6874b987c9629</id>
<content type='text'>
Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers</title>
<updated>2019-06-25T12:42:42Z</updated>
<author>
<name>Olof Johansson</name>
</author>
<published>2019-06-25T12:42:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=761d3d22fb74232d2a5a2899358ff1bab94d6fa0'/>
<id>urn:sha1:761d3d22fb74232d2a5a2899358ff1bab94d6fa0</id>
<content type='text'>
soc: tegra: Changes for v5.3-rc1

This contains a set of minor fixes and cleanups for core Tegra drivers.

* tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: Select pinctrl for Tegra194
  soc/tegra: fuse: Do not log error message on deferred probe
  soc/tegra: pmc: Add comments clarifying wake events
  soc/tegra: pmc: Avoid crash for non-wake IRQs
  soc/tegra: pmc: Fail to allocate more than one wake IRQ

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Select pinctrl for Tegra194</title>
<updated>2019-06-13T08:44:08Z</updated>
<author>
<name>Krishna Yarlagadda</name>
</author>
<published>2019-05-16T11:53:14Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=7ac13f6dcbd59b8f99395588cd7ef31f7e3bd3c6'/>
<id>urn:sha1:7ac13f6dcbd59b8f99395588cd7ef31f7e3bd3c6</id>
<content type='text'>
Select PINCTRL_TEGRA194 by default for Tegra194 SoC needed for
dynamically controlling PCIe pins.

Signed-off-by: Krishna Yarlagadda &lt;kyarlagadda@nvidia.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46Z</updated>
<author>
<name>Thomas Gleixner</name>
</author>
<published>2019-05-19T12:07:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1'/>
<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>soc/tegra: default select TEGRA_TIMER for Tegra210</title>
<updated>2019-02-23T11:13:45Z</updated>
<author>
<name>Joseph Lo</name>
</author>
<published>2019-02-21T07:21:45Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=f40f4fc9506d6b2b786920059b320aac3a831574'/>
<id>urn:sha1:f40f4fc9506d6b2b786920059b320aac3a831574</id>
<content type='text'>
The tegra timer is necessary for Tegra210 to support CPU idle power-down
state. So select it by default.

Signed-off-by: Joseph Lo &lt;josephl@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
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