kernel.git/drivers/soc/imx/gpcv2.c, branch linux-5.2.y

soc: imx: gpcv2: use devm_platform_ioremap_resource() to simplify code

2019-04-11T07:16:44Z

Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang Reviewed-by: Mukesh Ojha Signed-off-by: Shawn Guo

soc: imx: gpcv2: Make use of regmap_read_poll_timeout()

2019-03-19T08:47:09Z

Replace explicit polling loop with a call to regmap_read_poll_timeout() to avoid code repetition. Also fix misspelled "failed" while at it. Signed-off-by: Andrey Smirnov Cc: Lucas Stach Cc: Chris Healy Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: handle reset clocks

2019-01-11T07:12:59Z

Some power domains handled by the GPCv2 driver need to enable the clocks for devies inside the domain, so that the reset propagation and proper power-up sequencing happens. Handle them in the same way as on GPCv1. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo

soc: imx: gpcv2: handle additional power-down bits in handshake register

2019-01-11T07:12:38Z

Some of the i.MX8MQ domains have an additional control bit in the PU handshake (HSK) register. Documentation about this bit is a bit sparse at the moment, but it seems that it controls a power-down request to the AMBA domain bridge (ADB-400) attached to those domains. As the documentation doesn't desribe the usage of this bit yet, handle it in the same way as done in the ATF implementation. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: add support for i.MX8MQ SoC

2018-12-05T00:50:36Z

The GPCv2 on the Freescale i.MX8MQ SoC works in the same way as the GPCv2 on the i.MX7, but only controls more power domains with a different mapping. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo

soc: imx: gpcv2: move register access table to domain data

2018-12-05T00:50:34Z

The valid register ranges are defined by the implemented power domains, which are different between the individual SoCs where the GPCv2 is used. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: prefix i.MX7 specific defines

2018-12-05T00:50:19Z

So we can add i.MX8M support without introducing name clashes. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo

soc: imx: gpcv2: Switch to SPDX identifier

2018-10-01T05:24:15Z

Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo

soc: imx: gpcv2: make pgc driver more generic for other i.MX platforms

2018-10-01T05:24:14Z

i.MX8MQ and i.MX8MM share same gpc module with i.MX7D, they can reuse gpcv2 pgc driver for power domain control, this patch renames all functions and structure definitions started with "imx7" to "imx", and use .data in imx_gpcv2_dt_ids[] to pass platform specific power domain data for power domain driver, thus make gpcv2 pgc driver more generic for i.MX platforms. Signed-off-by: Anson Huang Acked-by: Andrey Smirnov Signed-off-by: Shawn Guo

soc: imx: gpcv2: use A_CORE instread of A7 for more i.MX platforms

2018-10-01T05:24:05Z

gpcv2 driver is NOT just used on i.MX7D which has Cortex-A7 cores, but also on i.MX8MQ/i.MX8MM platforms which use Cortex-A53 cores, so let's use A_CORE instread of A7 to avoid confusion. Signed-off-by: Anson Huang Acked-by: Andrey Smirnov Signed-off-by: Shawn Guo