kernel.git/drivers/soc/bcm, branch linux-5.10.y

soc: brcmstb: pm-arm: Fix refcount leak and __iomem leak bugs

2022-09-15T09:32:04Z

[ Upstream commit 1085f5080647f0c9f357c270a537869191f7f2a1 ] In brcmstb_pm_probe(), there are two kinds of leak bugs: (1) we need to add of_node_put() when for_each__matching_node() breaks (2) we need to add iounmap() for each iomap in fail path Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Liang He Link: https://lore.kernel.org/r/20220707015620.306468-1-windhl@126.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin

soc: bcm: brcmstb: pm: pm-arm: Fix refcount leak in brcmstb_pm_probe

2022-06-29T06:59:54Z

commit 37d838de369b07b596c19ff3662bf0293fdb09ee upstream. of_find_matching_node() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak. In brcmstb_init_sram, it pass dn to of_address_to_resource(), of_address_to_resource() will call of_find_device_by_node() to take reference, so we should release the reference returned by of_find_matching_node(). Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Miaoqian Lin Reviewed-by: Andy Shevchenko Signed-off-by: Florian Fainelli Signed-off-by: Greg Kroah-Hartman

soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines

2020-09-06T19:43:02Z

Change the RACPREFDATA(x) setting to prefetch the next 256-byte line after 4 consecutive lines have been used, instead of after 2 consecutive lines. This does improve the synthetic memcpy benchmark by an additional +0.5% on top of the previous change for Cortex-A72 CPUs. Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2

2020-09-04T20:48:49Z

Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs since this provides an average of a 3.8% performance increase for synthetic memcpy benchmarks. Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165

2020-09-04T20:48:42Z

72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164

2020-09-04T20:44:32Z

72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it according to the existing values we have. Signed-off-by: Florian Fainelli

soc: bcm: add BCM63xx power domain driver

2020-08-17T16:14:04Z

BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller to enable/disable certain components in order to save power. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Florian Fainelli Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache

2020-08-17T16:14:04Z

Brahma-B53 and Cortex-A72 CPUs integrated on Broadcom STB SoCs feature a read-ahead cache that performs cache line size adaptation between the bus interface unit and the memory controller. On 32-bit ARM kernels we have to resort to a full featured read-ahead cache driver under arch/arm/mm/cache-b15-rac.c (CONFIG_CACHE_B15_RAC) because there are still cache maintenance operations by set/ways/index that cannot be transparently handled by the ARM Coherency Extension that the read-ahead cache interfaces to. The 64-bit ARM kernel however has long deprecated all of those, so this is simply a one time configuration. Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Update programming for 7211

2020-01-05T21:44:04Z

Add a matching entry for 7211 which can be programmed with the same BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the function to include a72 in the name to reflect this applies to both types of 64-bit capable CPUs that we support (Brahma-B53 and Cortex-A72). Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211

2020-01-05T21:44:04Z

The BIUCTRL layout is a little different on 7211 which is equipped with a Cortex-A72, account for those register offset differences. We will match 7211 specifically in a subsequent commit. Signed-off-by: Florian Fainelli