kernel.git/drivers/powercap/intel_rapl_common.c, branch linux-5.11.y

powercap: RAPL: Add AMD Fam19h RAPL support

2020-11-10T18:59:07Z

AMD Family 19h's RAPL MSRs are identical to Family 17h's. Extend Family 17h's support to Family 19h. Signed-off-by: Kim Phillips Signed-off-by: Victor Ding Signed-off-by: Rafael J. Wysocki

powercap: Add AMD Fam17h RAPL support

2020-11-10T18:59:07Z

Enable AMD Fam17h RAPL support for the power capping framework. The support is as per AMD Fam17h Model31h (Zen2) and model 00-ffh (Zen1) PPR. Tested by comparing the results of following two sysfs entries and the values directly read from corresponding MSRs via /dev/cpu/[x]/msr: /sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj /sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj Signed-off-by: Victor Ding Acked-by: Kim Phillips [ rjw: Changelog edits ] Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: remove unneeded semicolon

2020-11-02T17:04:34Z

A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: enumerate Psys RAPL domain together with package RAPL domain

2020-10-16T15:35:36Z

On multi-package systems, the Psys MSR is only valid for CPUs on specific package (master package). The current code makes the assumption that package 0 is the master package, but this is not true on new platforms like SPR. Fix the problem by emuerating the Psys RAPL domain for every package, so CPUs in slave packages will read 0 for the Psys energy counter and only CPUs in master packages can get a valid reading and register the Psys RAPL domain. The sysfs I/F for the Psys RAPL domain is not changed. Signed-off-by: Zhang Rui [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: Fix domain detection

2020-10-16T15:35:36Z

As only the low 32 bits of the RAPL_DOMAIN_REG_STATUS register represents the energy counter, and the high 32 bits are reserved, detect the existence of a RAPL domain by checking the low 32 bits only. Signed-off-by: Zhang Rui Signed-off-by: Rafael J. Wysocki

powercap: RAPL: Add support for Lakefield

2020-09-16T12:16:04Z

Simply add Lakefield model ID. No additional changes are needed. Signed-off-by: Ricardo Neri [ rjw: Minor subject edit ] Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: add support for AlderLake

2020-09-10T17:17:29Z

Add intel_rapl support for the AlderLake platform. Signed-off-by: Zhang Rui Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: add support for RocketLake

2020-09-10T17:17:29Z

Add intel_rapl support for the RocketLake platform. Signed-off-by: Zhang Rui Signed-off-by: Rafael J. Wysocki

powercap/intel_rapl: add support for TigerLake Desktop

2020-09-10T17:17:29Z

Add intel_rapl support for the TigerLake desktop platform. Signed-off-by: Zhang Rui Signed-off-by: Rafael J. Wysocki

powercap: Add Power Limit4 support

2020-07-27T12:17:36Z

Modern Intel Mobile platforms support power limit4 (PL4), which is the SoC package level maximum power limit (in Watts). It can be used to preemptively limits potential SoC power to prevent power spikes from tripping the power adapter and battery over-current protection. This patch enables this feature by exposing package level peak power capping control to userspace via RAPL sysfs interface. With this, application like DTPF can modify PL4 power limit, the similar way of other package power limit (PL1). As this feature is not tested on previous generations, here it is enabled only for the platform that has been verified to work, for safety concerns. Signed-off-by: Sumeet Pawnikar Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Reviewed-by: Srinivas Pandruvada Tested-by: Srinivas Pandruvada Signed-off-by: Rafael J. Wysocki