kernel.git/drivers/platform/x86/intel/pmc, branch linux-6.6.y

platform/x86/intel: pmc: fix ltr decode in pmc_core_ltr_show()

2025-03-22T19:50:40Z

[ Upstream commit 583ef25bb2a094813351a727ddec38b35a15b9f8 ] In pmc_core_ltr_show(), promote 'val' to 'u64' to avoid possible integer overflow. Values (10 bit) are multiplied by the scale, the result of expression is in a range from 1 to 34,326,183,936 which is bigger then UINT32_MAX. Compile tested only. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Kandybka Reviewed-by: Rajneesh Bhardwaj Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20250123220739.68087-1-d.kandybka@gmail.com Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin

platform/x86/intel/pmc: Move GBE LTR ignore to suspend callback

2024-01-05T14:19:42Z

[ Upstream commit 70681aa0746ae61d7668b9f651221fad5e30c71e ] Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()") caused a network performance regression due to the GBE LTR ignore that it added at probe. This was needed in order to allow the SoC to enter the deepest Package C state. To fix the regression and at least support PC10 during suspend, move the LTR ignore from probe to the suspend callback, and enable it again on resume. This solution will allow PC10 during suspend but restrict Package C entry at runtime to no deeper than PC8/9 while a network cable it attach to the PCH LAN. Fixes: 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()") Signed-off-by: "David E. Box" Link: https://lore.kernel.org/r/20231223032548.1680738-6-david.e.box@linux.intel.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin

platform/x86/intel/pmc: Allow reenabling LTRs

2024-01-05T14:19:42Z

[ Upstream commit 6f9cc5c1f94daa98846b2073733d03ced709704b ] Commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()") caused a network performance regression due to the GBE LTR ignore that it added during probe. The fix will move the ignore to occur at suspend-time (so as to not affect suspend power). This will require the ability to enable the LTR again on resume. Modify pmc_core_send_ltr_ignore() to allow enabling an LTR. Fixes: 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()") Signed-off-by: "David E. Box" Link: https://lore.kernel.org/r/20231223032548.1680738-5-david.e.box@linux.intel.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin

platform/x86/intel/pmc: Add suspend callback

2024-01-05T14:19:42Z

[ Upstream commit 7c13f365aee68b01e7e68ee293a71fdc7571c111 ] Add a suspend callback to struct pmc for performing platform specific tasks before device suspend. This is needed in order to perform GBE LTR ignore on certain platforms at suspend-time instead of at probe-time and replace the GBE LTR ignore removal that was done in order to fix a bug introduced by commit 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()"). Fixes: 804951203aa5 ("platform/x86:intel/pmc: Combine core_init() and core_configure()") Signed-off-by: "David E. Box" Link: https://lore.kernel.org/r/20231223032548.1680738-4-david.e.box@linux.intel.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin

platform/x86/intel/pmc: Fix hang in pmc_core_send_ltr_ignore()

2024-01-01T12:42:26Z

[ Upstream commit fbcf67ce5a9e2831c14bdfb895be05213e611724 ] For input value 0, PMC stays unassigned which causes crash while trying to access PMC for register read/write. Include LTR index 0 in pmc_index and ltr_index calculation. Fixes: 2bcef4529222 ("platform/x86:intel/pmc: Enable debugfs multiple PMC support") Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20231216011650.1973941-1-rajvi.jingar@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin

x86/cpu: Fix Gracemont uarch

2023-08-09T19:51:06Z

Alderlake N is an E-core only product using Gracemont micro-architecture. It fits the pre-existing naming scheme perfectly fine, adhere to it. Signed-off-by: Peter Zijlstra (Intel) Acked-by: Rafael J. Wysocki Acked-by: Hans de Goede Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org

platform/x86:intel/pmc: Add Meteor Lake IOE-M PMC related maps

2023-06-20T10:51:08Z

Add device ID and register maps for the PMC in IO expansion die M in Meteor Lake. Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230613225347.2720665-9-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede

platform/x86:intel/pmc: Add Meteor Lake IOE-P PMC related maps

2023-06-20T10:51:08Z

Add device ID and register maps for the PMC in IO expansion die P in Meteor Lake. Signed-off-by: Xi Pardee Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230613225347.2720665-8-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede

platform/x86:intel/pmc: Use SSRAM to discover pwrm base address of primary PMC

2023-06-20T10:51:08Z

On older platforms, the base address for PMC was hardcoded in the driver. Newer platforms can now retrieve the base address from SSRAM. Use SSRAM to discover pwrm base address on Meteor Lake platform. If this method fails, it will fall back to the hardcoded value. Signed-off-by: Xi Pardee Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230613225347.2720665-7-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede

platform/x86:intel/pmc: Discover PMC devices

2023-06-20T10:51:08Z

On platforms with multiple PMCs, additional PMC devices are discovered in the SSRAM device associated with the primary PMC. Add support for discovering PMC devices from SSRAM. Use PMC devid to assign the corresponding register map. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Signed-off-by: Rajvi Jingar Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230613225347.2720665-6-rajvi.jingar@linux.intel.com Signed-off-by: Hans de Goede