kernel.git/drivers/pinctrl/intel/pinctrl-intel.c, branch linux-6.3.y

Merge tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2023-02-22T19:05:56Z

Pull pin control updates from Linus Walleij: "Nothing special, notably a lot of new Qualcomm hardware is supported, a RISC-V reference SoC and then some cleanups both in code and device tree bindings. Core changes: - Add PINCTRL_PINFUNCTION() macro and use it in several drivers New drivers: - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on) pin controllers. (RISC-V.) - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin controllers - New subdriver for the Qualcomm SA8775P SoC pin controller - New subdriver for the Qualcomm IPQ5332 SoC pin controller - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin control - New subdriver for the Mediatek MT7981 SoC pin controller Improvements: - Several cleanups and refactorings to the Intel drivers - Add 4KOhm bias support to the Intel driver - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver - Support general purpose clocks in the Qualcomm MSM8226 SoC - Several conversions to use the new I2C .probe_new() call - Massive clean-up of the Qualcomm Device Tree YAML schemas - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC driver" * tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits) pinctrl: qcom: Add support for i2c specific pull feature pinctrl: starfive: Add StarFive JH7110 aon controller driver pinctrl: starfive: Add StarFive JH7110 sys controller driver dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl pinctrl: add mt7981 pinctrl driver dt-bindings: pinctrl: add bindings for MT7981 SoC dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated pinctrl: qcom: Introduce IPQ5332 TLMM driver dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS pinctrl: at91: use devm_kasprintf() to avoid potential leaks dt-bindings: pinctrl: qcom: correct gpio-ranges in examples dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example ...

pinctrl: intel: Restore the pins that used to be in Direct IRQ mode

2023-02-07T09:13:51Z

If the firmware mangled the register contents too much, check the saved value for the Direct IRQ mode. If it matches, we will restore the pin state. Reported-by: Jim Minter Fixes: 6989ea4881c8 ("pinctrl: intel: Save and restore pins in "direct IRQ" mode") Tested-by: Jim Minter Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20230206141558.20916-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij

pinctrl: intel: Make use of struct pinfunction and PINCTRL_PINFUNCTION()

2022-12-30T08:22:52Z

Since pin control provides a generic data type and a macro for the pin function definition, use them in the Intel driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Define maximum pad number in the group

2022-12-28T12:20:19Z

Instead of using hard coded magic number here and there, define maximum pad number in the group in newly added INTEL_PINCTRL_MAX_GPP_SIZE. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Use same order of bit fields for PADCFG2

2022-12-28T12:20:18Z

PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Add ~4k bias support

2022-12-28T12:20:18Z

All versions that have 20k and 5k resistance, i.e. all that the driver supports, may support ~4k when the above mentioned are connected in parallel. Add such a support. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Add definitions to all possible biases

2022-12-28T12:20:18Z

Add definitions to all possible biases, i.e. add ~800 Ohms, ~952 Ohms, ~4 kOhms. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Deduplicate some code in intel_config_set_pull()

2022-12-28T12:20:18Z

First part is to assign default argument for all cases, since bias disablement doesn't use it anyway. Second part is to clear all bits in the bias setting and depending on the argument and parameter set them as asked. While at it, add break statement to the default cases. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Add default case to intel_config_set_pull()

2022-12-27T21:33:13Z

For the sake of symmetry with intel_config_get_pull(), add a default case to the outer switch. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: intel: Convert to generic_handle_domain_irq()

2022-12-27T19:21:04Z

Replace construct that matches generic_handle_irq(irq_find_mapping()) to a single call to generic_handle_domain_irq(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg