<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel.git/drivers/pinctrl/intel/pinctrl-cherryview.c, branch linux-4.0.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.0.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.0.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2015-03-10T08:02:23Z</updated>
<entry>
<title>pinctrl: update direction_output function of cherryview driver</title>
<updated>2015-03-10T08:02:23Z</updated>
<author>
<name>qipeng.zha</name>
</author>
<published>2015-03-03T10:13:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=549e783f6a1504fcd24576302bc3818538b677f0'/>
<id>urn:sha1:549e783f6a1504fcd24576302bc3818538b677f0</id>
<content type='text'>
From the comments of gpiod_direction_output(), need to set @value
as initial output, so update the lowlevel routine to make it work.

Signed-off-by: jason.cj.chen&lt;jason.cj.chen@intel.com&gt;
Signed-off-by: qipeng.zha &lt;qipeng.zha@intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs</title>
<updated>2015-02-04T08:59:26Z</updated>
<author>
<name>Mika Westerberg</name>
</author>
<published>2015-01-29T10:44:48Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=2479c7300ed943d62c88cd928ddccb4677c71ad4'/>
<id>urn:sha1:2479c7300ed943d62c88cd928ddccb4677c71ad4</id>
<content type='text'>
If the pin is in HiZ mode when it is requested as GPIO its value cannot be
read (it always returns 0). In order to cope with the Linux GPIO subsystem
where we do not have such state at all, turn the pin to be input instead.

Reported-by: Jerome Blin &lt;jerome.blin@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: drop owner assignment from platform_drivers</title>
<updated>2015-01-10T21:47:23Z</updated>
<author>
<name>Wolfram Sang</name>
</author>
<published>2014-12-21T21:14:36Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1ee68af8a5003bdda32ca02f93afc9701d50e871'/>
<id>urn:sha1:1ee68af8a5003bdda32ca02f93afc9701d50e871</id>
<content type='text'>
This platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang &lt;wsa@the-dreams.de&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: cherryview: Save and restore pin configs over system sleep</title>
<updated>2015-01-10T21:47:22Z</updated>
<author>
<name>Mika Westerberg</name>
</author>
<published>2014-12-04T10:32:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9eb457b547cc731bc2fc251bd79891a60c64fc3e'/>
<id>urn:sha1:9eb457b547cc731bc2fc251bd79891a60c64fc3e</id>
<content type='text'>
Before resuming from system sleep BIOS restores its view of pin
configuration. If we have configured some pins differently from that, for
instance some driver requested a pin as a GPIO but it was not in GPIO mode
originally, our view of the pin configuration will not match the hardware
state anymore.

This patch saves the pin configuration and interrupt mask registers on
suspend and restores them on exit. This should make sure that the
previously configured state is still in effect.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Add Intel Cherryview/Braswell pin controller support</title>
<updated>2014-11-04T10:21:02Z</updated>
<author>
<name>Mika Westerberg</name>
</author>
<published>2014-11-03T11:01:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6e08d6bbebebcf70f982d7190c4b6dc456cedd57'/>
<id>urn:sha1:6e08d6bbebebcf70f982d7190c4b6dc456cedd57</id>
<content type='text'>
This driver supports the pin/GPIO controllers found in newer Intel SoCs
like Cherryview and Braswell. The driver provides full GPIO support and
minimal set of pin controlling funtionality.

The driver is based on the original Cherryview GPIO driver authored by Ning
Li and Alan Cox.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
