kernel.git/drivers/pci/probe.c, branch linux-2.6.15.y

[PATCH] kernel-doc: PCI fixes

2005-10-28T22:37:01Z

PCI: add descriptions for missing function parameters. Eliminate all kernel-doc warnings here. Signed-off-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman

[PATCH] pci: fixup parent subordinate busnr

2005-09-23T15:05:16Z

I believe the change that broke things is introduction of pci_fixup_parent_subordinate_busnr(). The patch here does two things: - hunk #1 should fix the problems you've seen when you boot without additional "pci" kernel options; - hunk #2 supposedly fixes boot with "pci=assign-busses" option which otherwise hangs Acer TM81xx machines as reported. Please try this with and without "pci=assign-busses". If it boots, I'd like to see 'lspci -vvx' for both cases. Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] fix drivers/pci/probe.c warning

2005-09-22T14:58:25Z

This function expects an unsigned 32-bit type as its third argument: static u32 pci_size(u32 base, u32 maxbase, u32 mask) However, given these definitions: #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) these two calls in drivers/pci/probe.c are problematic for architectures for which a UL is not equivalent to a u32: sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK); sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK); Hence the below compile warning when building for ARCH=ppc64: drivers/pci/probe.c: In function `pci_read_bases': /.../probe.c:168: warning: large integer implicitly truncated to unsigned type /.../probe.c:218: warning: large integer implicitly truncated to unsigned type Here is a simple fix. Signed-off-by: Amos Waterland Signed-off-by: Greg Kroah-Hartman Signed-off-by: Linus Torvalds

[PATCH] Subject: PATCH: fix numa caused compile warnings

2005-09-10T17:06:21Z

pcibus_to_cpumask expands into more than just an initialiser so gcc moans about code before variable declarations. Signed-off-by: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] PCI: Small rearrangement of PCI probing code

2005-09-09T20:58:45Z

This patch makes some small rearrangements of the PCI probing code in order to make it possible for arch code to set up the PCI tree without needing to duplicate code from the PCI layer unnecessarily. PPC64 will use this to set up the PCI tree from the Open Firmware device tree, which we need to do on logically-partitioned pSeries systems. Signed-off-by: Paul Mackerras Signed-off-by: Greg Kroah-Hartman

[PATCH] PCI: Support PCM PM CAP version 3

2005-09-08T22:04:30Z

- support PCI PM CAP version 3 (as defined in PCI PM Interface Spec v1.2) - pci/probe.c sets the PM state initially to 4 which is D3cold. add a PCI_UNKNOWN - minor cleanups Signed-off-by: Daniel Ritz Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman

[PATCH] PCI: remove CONFIG_PCI_NAMES

2005-09-08T21:57:23Z

This patch removes CONFIG_PCI_NAMES. Signed-off-by: Adrian Bunk Signed-off-by: Greg Kroah-Hartman

[PATCH] PCI: remove PCI_BRIDGE_CTL_VGA handling from setup-bus.c

2005-07-29T20:12:51Z

The setup-bus code doesn't work correctly for configurations with more than one display adapter in the same PCI domain. This stuff actually is a leftover of an early 2.4 PCI setup code and apparently it stopped working after some "bridge_ctl" changes. So the best thing we can do is just to remove it and rely on the fact that any firmware *has* to configure VGA port forwarding for the boot display device properly. But then we need to ensure that the bus->bridge_ctl will always contain valid information collected at the probe time, therefore the following change in pci_scan_bridge() is needed. Signed-off-by: Ivan Kokshaysky Signed-off-by: Greg Kroah-Hartman Signed-off-by: Linus Torvalds

[PATCH] PCI: handle subtractive decode pci-pci bridge better

2005-07-01T20:35:50Z

With the number of PCI bus resources increased to 8, we can handle the subtractive decode PCI-PCI bridge like a normal bridge, taking into account standard PCI-PCI bridge windows (resources 0-2). This helps to avoid problems with peer-to-peer DMA behind such bridges, poor performance for MMIO ranges outside bridge windows and prefetchable vs. non-prefetchable memory issues. To reflect the fact that such bridges do forward all addresses to the secondary bus (transparency), remaining bus resources 3-7 are linked to resources 0-4 of the primary bus. These resources will be used as fallback by resource management code if allocation from standard bridge windows fails for some reason. Signed-off-by: Ivan Kokshaysky Acked-by: Dominik Brodowski Signed-off-by: Greg Kroah-Hartman

[PATCH] PCI: Fix up PCI routing in parent bridge

2005-07-01T20:35:49Z

When the cardbus bridge is behind another bridge change the routing in the parent bridge for new cards. This fixes Cardbus on various AMD64 laptops. Signed-off-by: Andi Kleen Signed-off-by: Greg Kroah-Hartman