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<title>kernel.git/drivers/pci/pcie, branch linux-4.15.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.
</subtitle>
<id>https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.15.y</id>
<link rel='self' href='https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.15.y'/>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/'/>
<updated>2018-03-24T10:02:48Z</updated>
<entry>
<title>PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics</title>
<updated>2018-03-24T10:02:48Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-17T20:26:42Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=18e595d70f17672f4744bc5a801e5cf1b402d778'/>
<id>urn:sha1:18e595d70f17672f4744bc5a801e5cf1b402d778</id>
<content type='text'>
[ Upstream commit 80d7d7a904fac3f8114448dbb8cc9fa253b10120 ]

Per PCIe r3.1, sec 5.5.1, LTR_L1.2_THRESHOLD determines whether we enter
the L1.2 Link state: if L1.2 is enabled and downstream devices have
reported that they can tolerate latency of at least LTR_L1.2_THRESHOLD, we
must enter L1.2 when CLKREQ# is de-asserted.

The implication is that LTR_L1.2_THRESHOLD is the time required to
transition the Link from L0 to L1.2 and back to L0, and per sec 5.5.3.3.1,
Figures 5-16 and 5-17, it appears that the absolute minimum time for those
transitions would be T(POWER_OFF) + T(L1.2) + T(POWER_ON) + T(COMMONMODE).

Therefore, compute LTR_L1.2_THRESHOLD as:

    2us T(POWER_OFF)
  + 4us T(L1.2)
  + T(POWER_ON)
  + T(COMMONMODE)
  = LTR_L1.2_THRESHOLD

Previously we set LTR_L1.2_THRESHOLD to a fixed value of 163840ns
(163.84us):

  #define LTR_L1_2_THRESHOLD_BITS     ((1 &lt;&lt; 21) | (1 &lt;&lt; 23) | (1 &lt;&lt; 30))
  ((1 &lt;&lt; 21) | (1 &lt;&lt; 23) | (1 &lt;&lt; 30)) = 0x40a00000
  LTR_L1.2_THRESHOLD_Value = (0x40a00000 &amp; 0x03ff0000) &gt;&gt; 16 = 0xa0 = 160
  LTR_L1.2_THRESHOLD_Scale = (0x40a00000 &amp; 0xe0000000) &gt;&gt; 29 = 0x2 (* 1024ns)
  LTR_L1.2_THRESHOLD = 160 * 1024ns = 163840ns

Obviously this doesn't account for the circuit characteristics of different
implementations.

Note that while firmware may enable LTR, Linux itself currently does not
enable LTR.  When L1.2 is enabled but LTR is not, LTR_L1.2_THRESHOLD is
ignored and we always enter L1.2 when it is enabled and CLKREQ# is
de-asserted.  So this patch should not have any effect unless firmware
enables LTR.

Fixes: f1f0366dd6be ("PCI/ASPM: Calculate and save the L1.2 timing parameters")
Link: https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Cc: Kenji Chen &lt;kenji.chen@intel.com&gt;
Cc: Patrick Georgi &lt;pgeorgi@google.com&gt;
Cc: Rajat Jain &lt;rajatja@google.com&gt;
Signed-off-by: Sasha Levin &lt;alexander.levin@microsoft.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci</title>
<updated>2017-11-15T23:01:28Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2017-11-15T23:01:28Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1b6115fbe3b3db746d7baa11399dd617fc75e1c4'/>
<id>urn:sha1:1b6115fbe3b3db746d7baa11399dd617fc75e1c4</id>
<content type='text'>
Pull PCI updates from Bjorn Helgaas:

  - detach driver before tearing down procfs/sysfs (Alex Williamson)

  - disable PCIe services during shutdown (Sinan Kaya)

  - fix ASPM oops on systems with no Root Ports (Ard Biesheuvel)

  - fix ASPM LTR_L1.2_THRESHOLD programming (Bjorn Helgaas)

  - fix ASPM Common_Mode_Restore_Time computation (Bjorn Helgaas)

  - fix portdrv MSI/MSI-X vector allocation (Dongdong Liu, Bjorn
    Helgaas)

  - report non-fatal AER errors only to the affected endpoint (Gabriele
    Paoloni)

  - distribute bus numbers, MMIO, and I/O space among hotplug bridges to
    allow more devices to be hot-added (Mika Westerberg)

  - fix pciehp races during initialization and surprise link down (Mika
    Westerberg)

  - handle surprise-removed devices in PME handling (Qiang)

  - support resizable BARs for large graphics devices (Christian König)

  - expose SR-IOV offset, stride, and VF device ID via sysfs (Filippo
    Sironi)

  - create SR-IOV virtfn/physfn sysfs links before attaching driver
    (Stuart Hayes)

  - fix SR-IOV "ARI Capable Hierarchy" restore issue (Tony Nguyen)

  - enforce Kconfig IOV/REALLOC dependency (Sascha El-Sharkawy)

  - avoid slot reset if bridge itself is broken (Jan Glauber)

  - clean up pci_reset_function() path (Jan H. Schönherr)

  - make pci_map_rom() fail if the option ROM is invalid (Changbin Du)

  - convert timers to timer_setup() (Kees Cook)

  - move PCI_QUIRKS to PCI bus Kconfig menu (Randy Dunlap)

  - constify pci_dev_type and intel_mid_pci_ops (Bhumika Goyal)

  - remove unnecessary pci_dev, pci_bus, resource, pcibios_set_master()
    declarations (Bjorn Helgaas)

  - fix endpoint framework overflows and BUG()s (Dan Carpenter)

  - fix endpoint framework issues (Kishon Vijay Abraham I)

  - avoid broken Cavium CN8xxx bus reset behavior (David Daney)

  - extend Cavium ACS capability quirks (Vadim Lomovtsev)

  - support Synopsys DesignWare RC in ECAM mode (Ard Biesheuvel)

  - turn off dra7xx clocks cleanly on shutdown (Keerthy)

  - fix Faraday probe error path (Wei Yongjun)

  - support HiSilicon STB SoC PCIe host controller (Jianguo Sun)

  - fix Hyper-V interrupt affinity issue (Dexuan Cui)

  - remove useless ACPI warning for Hyper-V pass-through devices (Vitaly
    Kuznetsov)

  - support multiple MSI on iProc (Sandor Bodo-Merle)

  - support Layerscape LS1012a and LS1046a PCIe host controllers (Hou
    Zhiqiang)

  - fix Layerscape default error response (Minghuan Lian)

  - support MSI on Tango host controller (Marc Gonzalez)

  - support Tegra186 PCIe host controller (Manikanta Maddireddy)

  - use generic accessors on Tegra when possible (Thierry Reding)

  - support V3 Semiconductor PCI host controller (Linus Walleij)

* tag 'pci-v4.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (85 commits)
  PCI/ASPM: Add L1 Substates definitions
  PCI/ASPM: Reformat ASPM register definitions
  PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
  PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
  PCI: xgene: Rename xgene_pcie_probe_bridge() to xgene_pcie_probe()
  PCI: xilinx: Rename xilinx_pcie_link_is_up() to xilinx_pcie_link_up()
  PCI: altera: Rename altera_pcie_link_is_up() to altera_pcie_link_up()
  PCI: Fix kernel-doc build warning
  PCI: Fail pci_map_rom() if the option ROM is invalid
  PCI: Move pci_map_rom() error path
  PCI: Move PCI_QUIRKS to the PCI bus menu
  alpha/PCI: Make pdev_save_srm_config() static
  PCI: Remove unused declarations
  PCI: Remove redundant pci_dev, pci_bus, resource declarations
  PCI: Remove redundant pcibios_set_master() declarations
  PCI/PME: Handle invalid data when reading Root Status
  PCI: hv: Use effective affinity mask
  PCI: pciehp: Do not clear Presence Detect Changed during initialization
  PCI: pciehp: Fix race condition handling surprise link down
  PCI: Distribute available resources to hotplug-capable bridges
  ...
</content>
</entry>
<entry>
<title>Merge tag 'modules-for-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux</title>
<updated>2017-11-15T21:46:33Z</updated>
<author>
<name>Linus Torvalds</name>
</author>
<published>2017-11-15T21:46:33Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=1be2172e96e33bfa22a5c7a651f768ef30ce3984'/>
<id>urn:sha1:1be2172e96e33bfa22a5c7a651f768ef30ce3984</id>
<content type='text'>
Pull module updates from Jessica Yu:
 "Summary of modules changes for the 4.15 merge window:

   - treewide module_param_call() cleanup, fix up set/get function
     prototype mismatches, from Kees Cook

   - minor code cleanups"

* tag 'modules-for-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux:
  module: Do not paper over type mismatches in module_param_call()
  treewide: Fix function prototypes for module_param_call()
  module: Prepare to convert all module_param_call() prototypes
  kernel/module: Delete an error message for a failed memory allocation in add_module_usage()
</content>
</entry>
<entry>
<title>Merge branch 'pci/portdrv' into next</title>
<updated>2017-11-14T18:11:24Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-14T18:11:24Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=8dceeaf8fff35a0b70a8cf3ca66883ac4bf4c9dd'/>
<id>urn:sha1:8dceeaf8fff35a0b70a8cf3ca66883ac4bf4c9dd</id>
<content type='text'>
* pci/portdrv:
  PCI/portdrv: Turn off PCIe services during shutdown
</content>
</entry>
<entry>
<title>Merge branch 'pci/msi' into next</title>
<updated>2017-11-14T18:11:23Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-14T18:11:23Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=6018182d3158505f11103adaee8ffb53424df986'/>
<id>urn:sha1:6018182d3158505f11103adaee8ffb53424df986</id>
<content type='text'>
* pci/msi:
  PCI/portdrv: Compute MSI/MSI-X IRQ vectors after final allocation
  PCI/portdrv: Factor out Interrupt Message Number lookup
  PCI/portdrv: Consolidate comments
  PCI/portdrv: Add #defines for AER and DPC Interrupt Message Number masks
</content>
</entry>
<entry>
<title>Merge branch 'pci/misc' into next</title>
<updated>2017-11-14T18:11:22Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-14T18:11:22Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=65a129d7847e4f5b24c6e56ab49090b1f6d0f3dc'/>
<id>urn:sha1:65a129d7847e4f5b24c6e56ab49090b1f6d0f3dc</id>
<content type='text'>
* pci/misc:
  PCI: Fix kernel-doc build warning
  PCI: Move PCI_QUIRKS to the PCI bus menu
  alpha/PCI: Make pdev_save_srm_config() static
  PCI: Remove unused declarations
  PCI: Remove redundant pci_dev, pci_bus, resource declarations
  PCI: Remove redundant pcibios_set_master() declarations
  PCI/PME: Handle invalid data when reading Root Status
  x86/pci/intel_mid_pci: Constify intel_mid_pci_ops and make it __initconst
  PCI: Constify pci_dev_type structure
</content>
</entry>
<entry>
<title>Merge branch 'pci/aspm' into next</title>
<updated>2017-11-14T18:11:20Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-14T18:11:20Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=9c42da50c068bd3f54cd6248efd9c92d118918ed'/>
<id>urn:sha1:9c42da50c068bd3f54cd6248efd9c92d118918ed</id>
<content type='text'>
* pci/aspm:
  PCI/ASPM: Add L1 Substates definitions
  PCI/ASPM: Reformat ASPM register definitions
  PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD
  PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time
  PCI/ASPM: Deal with missing root ports in link state handling
</content>
</entry>
<entry>
<title>PCI/ASPM: Add L1 Substates definitions</title>
<updated>2017-11-14T14:32:47Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-13T14:36:40Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=a48f3d5b197494d903c97ff7bc0909dac65740f8'/>
<id>urn:sha1:a48f3d5b197494d903c97ff7bc0909dac65740f8</id>
<content type='text'>
Add and use #defines for L1 Substate register fields instead of hard-coding
the masks.  Also update comments to use names from the spec.  No functional
change intended.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;</content>
</entry>
<entry>
<title>PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD</title>
<updated>2017-11-14T14:32:32Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-13T21:05:50Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=c00054f540bf81e592e1fee709b0bdbf20f478b5'/>
<id>urn:sha1:c00054f540bf81e592e1fee709b0bdbf20f478b5</id>
<content type='text'>
Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream)
device using the capability pointer of the *child* (downstream) device,
which corrupted some random word of the parent's config space.

Use the parent's L1 SS capability pointer to program its
LTR_L1.2_THRESHOLD.

Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings")
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
CC: stable@vger.kernel.org	# v4.11+
CC: Rajat Jain &lt;rajatja@google.com&gt;</content>
</entry>
<entry>
<title>PCI/ASPM: Account for downstream device's Port Common_Mode_Restore_Time</title>
<updated>2017-11-13T21:05:24Z</updated>
<author>
<name>Bjorn Helgaas</name>
</author>
<published>2017-11-13T14:50:30Z</published>
<link rel='alternate' type='text/html' href='https://git.0xinfinity.dev/distro/kernel.git/commit/?id=94ac327e043ee40d7fc57b54541da50507ef4e99'/>
<id>urn:sha1:94ac327e043ee40d7fc57b54541da50507ef4e99</id>
<content type='text'>
Every Port that supports the L1.2 substate advertises its Port
Common_Mode_Restore_Time, i.e., the time the Port requires to re-establish
common mode when exiting L1.2 (see PCIe r3.1, sec 7.33.2).

Per sec 5.5.3.3.1, when exiting L1.2, the Downstream Port (the device at
the upstream end of the link) must send TS1 training sequences for at least
T(COMMONMODE) after it detects electrical idle exit on the Link.  We want
this to be long enough for both ends of the Link, so we should set it to
the maximum of the Port Common_Mode_Restore_Time for the upstream and
downstream components on the Link.

Previously we only looked at the Port Common_Mode_Restore_Time of the
upstream device, so if the downstream device required more time, we didn't
program the upstream device's T(COMMONMODE) correctly.

Fixes: f1f0366dd6be ("PCI/ASPM: Calculate and save the L1.2 timing parameters")
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Acked-by: Rajat Jain &lt;rajatja@google.com&gt;
CC: stable@vger.kernel.org	# v4.11+</content>
</entry>
</feed>
