kernel.git/drivers/pci/iov.c, branch linux-4.5.y

Merge branches 'pci/aer', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and 'pci/virtualization' into next

2015-11-02T21:57:03Z

* pci/aer: PCI/AER: Clear error status registers during enumeration and restore * pci/hotplug: PCI: pciehp: Queue power work requests in dedicated function * pci/misc: PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum x86/PCI: Make pci_subsys_init() static PCI: Add builtin_pci_driver() to avoid registration boilerplate PCI: Remove unnecessary "if" statement * pci/msi: x86/PCI: Don't alloc pcibios-irq when MSI is enabled PCI/MSI: Export all remapped MSIs to sysfs attributes PCI: Disable MSI on SiS 761 * pci/resource: sparc/PCI: Add mem64 resource parsing for root bus PCI: Expand Enhanced Allocation BAR output PCI: Make Enhanced Allocation bitmasks more obvious PCI: Handle Enhanced Allocation capability for SR-IOV devices PCI: Add support for Enhanced Allocation devices PCI: Add Enhanced Allocation register entries PCI: Handle IORESOURCE_PCI_FIXED when assigning resources PCI: Handle IORESOURCE_PCI_FIXED when sizing resources PCI: Clear IORESOURCE_UNSET when reverting to firmware-assigned address * pci/virtualization: PCI: Fix sriov_enable() error path for pcibios_enable_sriov() failures PCI: Wait 1 second between disabling VFs and clearing NumVFs PCI: Reorder pcibios_sriov_disable() PCI: Remove VFs in reverse order if virtfn_add() fails PCI: Remove redundant validation of SR-IOV offset/stride registers PCI: Set SR-IOV NumVFs to zero after enumeration PCI: Enable SR-IOV ARI Capable Hierarchy before reading TotalVFs PCI: Don't try to restore VF BARs

PCI: Fix sriov_enable() error path for pcibios_enable_sriov() failures

2015-10-30T20:15:02Z

Disable VFs if pcibios_enable_sriov() fails, just like we do for other errors in sriov_enable(). Call pcibios_sriov_disable() if virtfn_add() fails. [bhelgaas: changelog, split to separate patch for reviewability] Fixes: 995df527f399 ("PCI: Add pcibios_sriov_enable() and pcibios_sriov_disable()") Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas Reviewed-by: Wei Yang

PCI: Wait 1 second between disabling VFs and clearing NumVFs

2015-10-30T20:14:56Z

Per sec 3.3.3.1 of the SR-IOV spec, r1.1, we must allow 1.0s after clearing VF Enable before reading any field in the SR-IOV Extended Capability. Wait 1 second before calling pci_iov_set_numvfs(), which reads PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE after it sets PCI_SRIOV_NUM_VF. [bhelgaas: split to separate patch for reviewability, add spec reference] Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas

PCI: Reorder pcibios_sriov_disable()

2015-10-30T20:14:33Z

Move pcibios_sriov_disable() up so it's defined before a future use. [bhelgaas: split to separate patch for reviewability] Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas Reviewed-by: Wei Yang

PCI: Remove VFs in reverse order if virtfn_add() fails

2015-10-30T20:14:00Z

If virtfn_add() fails, we call virtfn_remove() for any previously added devices. Remove the devices in reverse order (first-added is last-removed), which is more natural and doesn't require an additional variable. [bhelgaas: changelog, split to separate patch for reviewability] Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas Reviewed-by: Wei Yang

PCI: Handle Enhanced Allocation capability for SR-IOV devices

2015-10-29T22:35:40Z

SR-IOV BARs can be specified via EA entries. Extend the EA parser to extract the SRIOV BAR resources, and modify sriov_init() to use resources previously obtained via EA. Signed-off-by: David Daney Signed-off-by: Bjorn Helgaas Acked-by: Sean O. Stalley

PCI: Remove redundant validation of SR-IOV offset/stride registers

2015-10-29T21:20:57Z

Previously, we read, validated, and cached PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE in sriov_enable(). But sriov_init() now does that via compute_max_vf_buses(), so we don't need to do it again. Remove the PCI_SRIOV_VF_OFFSET and PCI_SRIOV_VF_STRIDE config reads from sriov_enable(). The pci_sriov structure already contains the offset and stride corresponding to the current NumVFs. [bhelgaas: split to separate patch for reviewability] Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas Reviewed-by: Wei Yang

PCI: Set SR-IOV NumVFs to zero after enumeration

2015-10-29T21:20:50Z

The enumeration path should leave NumVFs set to zero. But after 4449f079722c ("PCI: Calculate maximum number of buses required for VFs"), we call virtfn_max_buses() in the enumeration path, which changes NumVFs. This NumVFs change is visible via lspci and sysfs until a driver enables SR-IOV. Iterate from TotalVFs down to zero so NumVFs is zero when we're finished computing the maximum number of buses. Validate offset and stride in the loop, so we can test it at every possible NumVFs setting. Rename virtfn_max_buses() to compute_max_vf_buses() to hint that it does have a side effect of updating iov->max_VF_buses. [bhelgaas: changelog, rename, allow numVF==1 && stride==0, rework loop, reverse sense of error path] Fixes: 4449f079722c ("PCI: Calculate maximum number of buses required for VFs") Based-on-patch-by: Ethan Zhao Signed-off-by: Alexander Duyck Signed-off-by: Bjorn Helgaas

PCI: Enable SR-IOV ARI Capable Hierarchy before reading TotalVFs

2015-10-29T21:20:31Z

For some SR-IOV devices, the number of available virtual functions, i.e., TotalVFs, increases after setting the ARI Capable Hierarchy bit in the SR-IOV Control register. This violates the SR-IOV spec, r1.1, sec 3.3.6, which says TotalVFs is HwInit, but we don't need TotalVFs before setting the ARI Capable bit anyway. Set the ARI Capable Hierarchy bit (if ARI is enabled in the upstream bridge) before reading TotalVFs. [bhelgaas: changelog] Signed-off-by: Ben Shelton Signed-off-by: Bjorn Helgaas

PCI: Add pcibios_iov_resource_alignment() interface

2015-03-31T02:02:36Z

Per the SR-IOV spec r1.1, sec 3.3.14, the required alignment of a PF's IOV BAR is the size of an individual VF BAR, and the size consumed is the individual VF BAR size times NumVFs. The PowerNV platform has additional alignment requirements to help support its Partitionable Endpoint device isolation feature (see Documentation/powerpc/pci_iov_resource_on_powernv.txt). Add a pcibios_iov_resource_alignment() interface to allow platforms to request additional alignment. [bhelgaas: changelog, adapt to reworked pci_sriov_resource_alignment(), drop "align" parameter] Signed-off-by: Wei Yang Acked-by: Bjorn Helgaas Signed-off-by: Benjamin Herrenschmidt