Hosts the 0x221E linux distro kernel. https://git.0xinfinity.dev/distro/kernel.git/atom?h=linux-4.10.y 2016-12-07T20:34:58Z 2016-12-07T20:34:58Z Bjorn Helgaas 2016-12-06T20:27:59Z urn:sha1:ca5ab37b19dfd1d77787d0474b767ec1185670f4 Add Makefile comments to explain the Kconfig and build strategy for ARM64 drivers that work around not-quite-ECAM issues. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-12-06T19:45:50Z Duc Dang 2016-12-02T02:27:07Z urn:sha1:c5d4603961009c39de94725213d8b5420f110f9e PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to configure additional controller's register to address device at bus:dev:function. Add a quirk to discover controller MMIO register space and configure controller registers to select and address the target secondary device. The quirk will only be applied for X-Gene PCIe MCFG table with OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs). Tested-by: Jon Masters <jcm@redhat.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-12-06T19:45:50Z Tomasz Nowicki 2016-12-01T05:16:34Z urn:sha1:648d93fc77da4f655cf13108417f33c91d745e2c ThunderX pass1.x requires to emulate the EA headers for on-chip devices hence it has to use custom pci_thunder_ecam_ops for accessing PCI config space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it can be applied while probing ACPI based PCI host controller. ThunderX pass1.x is using the same way for accessing off-chip devices (so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries too. Quirk is considered for ThunderX silicon pass1.x only which is identified via MCFG revision 2. ThunderX pass 1.x requires the following accessors: NUMA node 0 PCI segments 0- 3: pci_thunder_ecam_ops (MCFG quirk) NUMA node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk) NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk) [bhelgaas: change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_ECAM] Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-12-06T19:45:49Z Tomasz Nowicki 2016-12-01T06:07:56Z urn:sha1:44f22bd91e88f9a1203a6e564a237e593f5f2f74 ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully compliant with ECAM standard. It uses non-standard configuration space accessors (see thunder_pem_ecam_ops) and custom configuration space granulation (see bus_shift = 24). In order to access configuration space and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk infrastructure. This involves: 1. A new thunder_pem_acpi_init() init function to locate PEM-specific register ranges using ACPI. 2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk code. 3. New quirk entries for each PEM segment. Each contains platform IDs, mentioned thunder_pem_ecam_ops and CFG resources. Quirk is considered for ThunderX silicon pass2.x only which is identified via MCFG revision 1. ThunderX pass 2.x requires the following accessors: NUMA Node 0 PCI segments 0- 3: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk) NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant) NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk) [bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM] Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-12-06T19:45:49Z Dongdong Liu 2016-12-01T06:45:35Z urn:sha1:5f00f1a0178cf52928366a5e1f376a65f1f3f389 The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely ECAM-compliant. It is non-ECAM only for the RC bus config space; for any other bus underneath the root bus it does support ECAM access. Add specific quirks for PCI config space accessors. This involves: 1. New initialization call hisi_pcie_init() to obtain RC base addresses from PNP0C02 at the root of the ACPI namespace (under \_SB). 2. New entry in common quirk array. [bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't depend on CONFIG_PCI_HISI] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2016-10-05T19:00:21Z Bjorn Helgaas 2016-10-05T19:00:21Z urn:sha1:bdf530984d10b6b88b10a6d03057409a3f1c6897 * pci/host-vmd: x86/PCI: VMD: Move VMD driver to drivers/pci/host x86/PCI: VMD: Synchronize with RCU freeing MSI IRQ descs x86/PCI: VMD: Eliminate index member from IRQ list x86/PCI: VMD: Eliminate vmd_vector member from list type x86/PCI: VMD: Convert to use pci_alloc_irq_vectors() API x86/PCI: VMD: Allocate IRQ lists with correct MSI-X count PCI: Use positive flags in pci_alloc_irq_vectors() PCI: Update "pci=resource_alignment" documentation Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile 2016-10-04T17:26:37Z Keith Busch 2016-10-04T17:26:37Z urn:sha1:181ffd19cc9898f795646bf9a897072a419a51ed Move the driver source and Kconfig to the PCI host bridge drivers directory and move the config option to a more appropriate sub-menu instead of occupying the top-level location. Update the Kconfig option with the X86_64 dependency that was implicitly included from the previous location, and add information about the module name when built as a loadable module. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jon Derrick <jonathan.derrick@intel.com> 2016-09-03T16:41:09Z Shawn Lin 2016-09-03T16:41:09Z urn:sha1:e77f847df54c6b01f4628dd352f4168db3082aa8 Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> 2016-08-01T17:32:13Z Bjorn Helgaas 2016-08-01T17:32:13Z urn:sha1:a04bee8285a71cdbb9076c3dc38be1f0b9a6b4b3 * pci/host-aardvark: arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700 PCI: aardvark: Add Aardvark PCI host controller driver dt-bindings: add DT binding for the Aardvark PCIe controller * pci/host-altera: PCI: altera: Poll for link up status after retraining the link PCI: altera: Check link status before retrain link PCI: altera: Reorder read/write functions * pci/host-dra7xx: PCI: dra7xx: Fix return value in case of error * pci/host-hv: PCI: hv: Fix interrupt cleanup path PCI: hv: Handle all pending messages in hv_pci_onchannelcallback() PCI: hv: Don't leak buffer in hv_pci_onchannelcallback() * pci/host-vmd: x86/PCI: VMD: Separate MSI and MSI-X vector sharing x86/PCI: VMD: Use x86_vector_domain as parent domain x86/PCI: VMD: Use lock save/restore in interrupt enable path x86/PCI: VMD: Initialize list item in IRQ disable x86/PCI: VMD: Select device dma ops to override * pci/host-xilinx: PCI: xilinx: Fix return value in case of error Manually apply changes from pci/demodularize-hosts and pci/host-request-windows to drivers/pci/host/pci-aardvark.c 2016-07-26T21:05:11Z Thomas Petazzoni 2016-06-30T09:32:31Z urn:sha1:8c39d710363c14ecb09219332869707395d1d495 Add a driver for the Aardvark PCIe controller used on the Marvell Armada 3700 ARM64 SoC. Based on work done by Hezi Shahmoon <hezi.shahmoon@marvell.com> and Marcin Wojtas <mw@semihalf.com>. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>